Datasheet

V
+
V
-
V
OCM
Input
60 k:
60 k:
Internal
Circuitry
LMP8350
www.ti.com SNOSB80B –FEBRUARY 2011–REVISED MARCH 2013
The voltage at the EN pin can be generated with a resistive voltage divider or a buffer connected to a voltage
source or a DAC. The schematic diagram below shows how to generate EN voltage with a resistive voltage
divider.
Values of R
A
and R
B
can be calculated to achieve the voltages in Table 2, however their sum should be below
50kΩ to keep the voltage at the enable pin stable. Recommended values for Ra and Rb are given in Table 3.
Table 3. Recommended Ra and Rb for Mode Selection
Mode 10V 6.6V 5V V
EN
High Power R
A
=0 R
A
=0 R
A
=0 >7/8 V
S
R
B
=inf R
B
=inf R
B
=inf
Med Power R
A
=18K R
A
=18K R
A
=18K 5/8 V
S
R
B
=30K R
B
=30K R
B
=30K
Low Power R
A
=33K R
A
=33K R
A
=33K 3/8 V
S
R
B
=18K R
B
=18K R
B
=18K
Shutdown R
A
=Inf R
A
=Inf R
A
=Inf <1/8 V
S
R
B
=0 R
B
=0 R
B
=0
V
OCM
PIN AND OUTPUT COMMON MODE SETTING
Output common mode voltage is set by the V
OCM
pin. Both outputs will be offset in the same direction (phase) by
an amount equal to the applied V
OCM
voltage.
The V
OCM
pin, if left unconnected, will self-bias to mid-supply . Two internal 60KΩ resistors set this midpoint.
These resistors are shown in Figure 29.
Figure 29. V
OCM
Internal Bias Circuit
The equivalent resistance looking into the V
OCM
pin will look like 30KΩ to mid supply, plus about ±700nA for
internal base currents (which scales with power mode and supply current). If left floating, the V
OCM
input should
be bypassed to ground with a 0.1 µF ceramic capacitor.
If a different output common mode voltage is desired, the V
OCM
pin should be driven by a clean, low impedance
source to override the internal divider resistors. The V
OCM
pin should be bypassed to ground with a 0.1 µF
ceramic capacitor. It should be noted that any signal or noise coupling into the V
OCM
will be passed as common
mode noise and may result in the loss of dynamic range, degraded CMRR, degraded balance and higher
distortion. The V
OCM
pin is primarily intended as a DC bias path and is not intended for use as a signal path.
For applications that can tolerate slight shifts in the V
OCM
voltage over temperature, it is also possible to use a
single resistor to program the V
OCM
voltage by paralleling one of the internal resistors to change the ratio.
FULL BANDWIDTH LIMITATIONS
Although the LMP8350 has a unity gain bandwidth of over 200MHz, it is primarily intended for lower sample rate,
high-precision ADC’s with baseband analog input signal bandwidths in the DC to <1MHz range (not to be
confused with sampling rate). The LMP8350's high open loop bandwidth is used to provide ultra low-distortion
and fast settling times. Maximum power bandwidth is limited by the internal output common mode feedback path,
which is limited to 1MHz to 5MHz. Operation with input signals above 1MHz with near full output swings can
cause random shifts in the output common mode and possible AC instabilities. For this reason, the LMP8350 is
not intended to be used wide bandwidth (>1MHz) signal paths. Single ended inputs rely on the common mode
signal path and will have a bandwidth limited to that of the internal common mode buffer.
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