Datasheet

FREQUENCY (Hz)
GAIN (dB) AND PHASE (°)
100
80
60
40
20
0
-20
1k 10k 100k 1M 10M 100M
Gain
Phase
G
MIN
f
2
f
2
/10
1/F
LMP7707, LMP7708, LMP7709
SNOSAW5B –JUNE 2007–REVISED MARCH 2013 www.ti.com
Note that the constraint 1/F ≥ G
min
needs to be satisfied only in the vicinity of the intersection of G and 1/F; 1/F
can be shaped elsewhere as needed. Two rules must be satisfied in order to maintain adequate phase margin.
Rule 1The plot of 1/F should intersect with the plot of the open loop gain at a value larger than G
MIN
. At that
point, the open loop gain G has a phase margin of 45°.
The location f
2
in Figure 59 illustrates the proper intersection point for the LMP7707/LMP7708/LMP7709
using the circuit of Figure 58. The intersection of G and 1/F at the op amp's second pole location is the
45° phase margin reference point.
Rule 2The 1/F pole (see Figure 59) should be positioned at the frequency that is at least one decade below the
intersection point f
2
of 1/F and G. This positioning takes full advantage of the 90° of phase lead brought
about by the 1/F pole. This additional phase lead accompanies the increase in magnitude of 1/F observed
at frequencies greater than the 1/F pole.
The resulting system has approximately 45° of phase margin, based upon the fact that the open loop gain's
dominant pole and the second pole are more than one decade apart and that the open loop gain has no other
pole within one decade of its intersection point with 1/F. If there is a third pole in the open loop gain G at a
frequency greater than f
2
and if it occurs less than a decade above that frequency, then there will be an effect on
phase margin.
DESIGN EXAMPLE
The input lead-lag compensation method can be applied to an application using the LMP7707, LMP7708 or
LMP7709 in an inverting configuration, as shown in Figure 58.
Figure 59. LMP7707 Open Loop Gain and 1/F Lead-Lag Feedback Network.
Figure 59 shows that G
MIN
= 16 dB and f
2
(intersection point) = 2.4 MHz.
A gain of 6 dB (or a magnitude of –1) is well below the LMP7707’s G
MIN
. Without external lead-lag compensation,
the inverse feedback factor is found using Equation 4 which applies to both inverting and non-inverting
configurations. Unity gain implementation for the inverting configuration means R
F
= R
1
, and 1/F = 2 (6 dB).
Procedure:
The compensation circuit shown in Figure 58 is implemented. The inverse feedback function is shaped by the
solid line in Figure 59. The 1/F plot is 6 dB at low frequencies. At higher frequencies, it is made to intersect the
loop gain G at frequency f
2
with gain amplitude of 16 dB (G
MIN
), which equals a magnitude of six times. This
follows the recommendations in Rule 1. The 1/F pole f
p
is set one decade below the intersection point (f
2
= 2.4
MHz) as given in Rule 2, and results in a frequency f
p
= 240 kHz. The next steps should be taken to calculate the
values of the compensation components:
Step 1)Set 1/F equal to G
MIN
using Equation 17. This gives a value for resistor R
C
.
Step 2)Set the 1/F pole one decade below the intersection point using Equation 14. This gives a value for
capacitor C.
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Product Folder Links: LMP7707 LMP7708 LMP7709