Datasheet

ESD
R
1
IN
+
ESD
D
1
D
2
R
2
ESD
IN
-
ESD
V
+
V
-
V
-
V
+
1k
10k 100k 1M 10M
FREQUENCY (Hz)
-10
-8
-6
-4
-2
0
2
NORMALIZED GAIN (dB)
V
S
= 5V
R
1
= R
2
= 100 k:
A
V
= -1
C
F
= 5 pF
C
F
= 3 pF
C
F
= 1 pF
C
F
= 0 pF
(1 - A
V
)
2
2A
0
A
V
C
IN
<
R
1
LMP7701, LMP7702, LMP7704
SNOSAI9H –SEPTEMBER 2005–REVISED MARCH 2013 www.ti.com
Equation 1 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. In order to
eliminate this effect, the poles should be placed in Butterworth position, since poles in Butterworth position do not
cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 1 should be
set to equal −1. Using this fact and the relation between R
1
and R
2
, R
2
= −A
V
R
1
, the optimum value for R
1
can
be found. This is shown in Equation 2. If R
1
is chosen to be larger than this optimum value, gain peaking will
occur.
(2)
In Figure 46, C
F
is added to compensate for input capacitance and to increase stability. Additionally, C
F
reduces
or eliminates the gain peaking that can be caused by having a larger feedback resistor. Figure 48 shows how C
F
reduces gain peaking.
Figure 48. Closed Loop Gain vs. Frequency with Compensation
DIODES BETWEEN THE INPUTS
The LMP7701/LMP7702/LMP7704 have a set of anti-parallel diodes between the input pins, as shown in
Figure 49. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the
amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode
voltage drop might damage the diodes. The differential signal between the inputs needs to be limited to ±300 mV
or the input current needs to be limited to ±10 mA.
Figure 49. Input of LMP7701
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