Datasheet

L M K 0 4 8 1 6 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU107
68
3) Confirm PLL2 operation/locking
1) Program LD_MUX = “PLL2_R/2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, examine PLL2_R programming.
ii. If not, examine physical OSCin input.
3) Program LD_MUX = “PLL2_N/2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, confirm OSCin_FREQ is programmed to OSCin frequency.
ii. If not, examine PLL2_N programming.
Naturally, the output frequency of the above two items should be the same frequency.
5) Program LD_MUX = “PLL2 DLD”
6) Confirm the LD pin output is high.
7) Program LD_MUX = “PLL1 & PLL2 DLD”
8) Confirm the LD pin output is high.