Datasheet

L M K 0 4 8 1 6 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU107
3
LMK04816B CLKout Phase Noise ........................................................................................................................ 40
LMK04816B OSCout Phase Noise ....................................................................................................................... 41
APPENDIX C: SCHEMATICS ................................................................................................................................... 43
POWER SUPPLIES ......................................................................................................................................................... 43
LMK04816B DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS ......................................................................................... 44
REFERENCE INPUTS (CLKIN0, CLKIN1, & CLKIN2), EXTERNAL VCXO (OSCIN) & VCO CIRCUITS ............................................... 45
CLOCK OUTPUTS (OSCOUT0, CLKOUT0 TO CLKOUT3) ...................................................................................................... 46
CLOCK OUTPUTS (CLKOUT4 TO CLKOUT7) ...................................................................................................................... 47
CLOCK OUTPUTS (CLKOUT8 TO CLKOUT11) .................................................................................................................... 48
UWIRE HEADER, LOGIC I/O PORTS AND STATUS LEDS........................................................................................................ 49
USB INTERFACE........................................................................................................................................................... 50
APPENDIX D: BILL OF MATERIALS ........................................................................................................................ 51
APPENDIX E: PCB LAYERS STACKUP ..................................................................................................................... 56
APPENDIX F: PCB LAYOUT .................................................................................................................................... 57
LAYER #1 – TOP .......................................................................................................................................................... 57
LAYER #2 – RF GROUND PLANE (INVERTED) ..................................................................................................................... 58
LAYER #3 – VCC PLANES ............................................................................................................................................... 59
LAYER #4 – GROUND PLANE (INVERTED) .......................................................................................................................... 60
LAYER # 5 – VCC PLANES 2 ............................................................................................................................................ 61
LAYER #6 – BOTTOM .................................................................................................................................................... 62
LAYERS #1 AND 6 – TOP AND BOTTOM (COMPOSITE) ......................................................................................................... 63
APPENDIX G: PROPERLY CONFIGURING LPT PORT ............................................................................................... 65
LPT DRIVER LOADING ................................................................................................................................................... 65
CORRECT LPT PORT/ADDRESS ....................................................................................................................................... 65
CORRECT LPT MODE .................................................................................................................................................... 66
APPENDIX H: TROUBLESHOOTING INFORMATION ............................................................................................... 67
1) CONFIRM COMMUNICATIONS ............................................................................................................................... 67
2) CONFIRM PLL1 OPERATION/LOCKING .................................................................................................................... 67
3) CONFIRM PLL2 OPERATION/LOCKING .................................................................................................................... 68