Datasheet

L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
3
CLOCK OUTPUTS (CLKOUT) ........................................................................................................................................... 40
LMK04808B CLKout Phase Noise ........................................................................................................................ 40
LMK04808B OSCout Phase Noise ....................................................................................................................... 42
LMK04806B CLKout Phase Noise ........................................................................................................................ 43
LMK04806B OSCout Phase Noise ....................................................................................................................... 45
LMK04803B CLKout Phase Noise ........................................................................................................................ 46
LMK04803B OSCout Phase Noise ....................................................................................................................... 48
APPENDIX C: SCHEMATICS ................................................................................................................................... 49
POWER SUPPLIES ......................................................................................................................................................... 49
LMK048XXB DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS .......................................................................................... 50
REFERENCE INPUTS (CLKIN0 & CLKIN1), EXTERNAL VCXO (OSCIN) & VCO CIRCUITS, AND OSCOUT1 OUTPUT ......................... 51
CLOCK OUTPUTS (OSCOUT0, CLKOUT0 TO CLKOUT3) ...................................................................................................... 52
CLOCK OUTPUTS (CLKOUT4 TO CLKOUT7) ...................................................................................................................... 53
CLOCK OUTPUTS (CLKOUT8 TO CLKOUT11) .................................................................................................................... 54
UWIRE HEADER, LOGIC I/O PORTS AND STATUS LEDS........................................................................................................ 55
USB INTERFACE........................................................................................................................................................... 56
APPENDIX D: BILL OF MATERIALS ........................................................................................................................ 57
APPENDIX E: PCB LAYERS STACKUP ..................................................................................................................... 66
APPENDIX F: PCB LAYOUT .................................................................................................................................... 67
LAYER #1 – TOP .......................................................................................................................................................... 67
LAYER #2 – RF GROUND PLANE (INVERTED) ..................................................................................................................... 68
LAYER #3 – VCC PLANES ............................................................................................................................................... 69
LAYER #4 – GROUND PLANE (INVERTED) .......................................................................................................................... 70
LAYER # 5 – VCC PLANES 2 ............................................................................................................................................ 71
LAYER #6 – BOTTOM .................................................................................................................................................... 72
LAYERS #1 AND 6 – TOP AND BOTTOM (COMPOSITE) ......................................................................................................... 73
APPENDIX G: PROPERLY CONFIGURING LPT PORT ............................................................................................... 74
LPT DRIVER LOADING ................................................................................................................................................... 74
CORRECT LPT PORT/ADDRESS ....................................................................................................................................... 74
CORRECT LPT MODE .................................................................................................................................................... 75
APPENDIX H: TROUBLESHOOTING INFORMATION ............................................................................................... 76
1) CONFIRM COMMUNICATIONS ............................................................................................................................... 76
2) CONFIRM PLL1 OPERATION/LOCKING .................................................................................................................... 76
3) CONFIRM PLL2 OPERATION/LOCKING .................................................................................................................... 77