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LMK048XX EVALUATION BOARD OPERATING INSTRUCTIONS

LMK04800 Family

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

LMK048xx Evaluation Board Operating Instructions

National Semiconductor Corporation

High Speed Products Division

Precision Timing Devices

January 2012

Summary of content (79 pages)

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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs LMK048xx Evaluation Board Operating Instructions National Semiconductor Corporation High Speed Products Division Precision Timing Devices January 2012 1
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Table of Contents TABLE OF CONTENTS.............................................................................................................................................. 2 GENERAL DESCRIPTION .......................................................................................................................................... 4 EVALUATION BOARD KIT CONTENTS ................................................
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CLOCK OUTPUTS (CLKOUT) ...........................................................................................................................................40 LMK04808B CLKout Phase Noise ........................................................................................................................40 LMK04808B OSCout Phase Noise .........................................................................
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S General Description The LMK048xx Evaluation Board simplifies evaluation of the LMK048xxB Low-Noise Clock Jitter Cleaner with Dual Loop PLLs. National Semiconductor‟s CodeLoader software can be used to program the internal registers of the LMK048xxB device through the MICROWIRETM interface. The CodeLoader software will run on a Windows 2000 or Windows XP PC and can be downloaded from http://www.national.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Quick Start Full evaluation board instructions are downloadable from the LMK048xxB device product folder at www.national.com. 1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard LP3878-ADJ LDO regulator will output a low-noise 3.3 V supply to operate the device. 2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 122.88 MHz for default.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Default CodeLoader Modes for Evaluation Boards CodeLoader saves the state of the selected LMK048xxB device when exiting the software. To ensure a common starting point, the following modes listed in Table 3 may be restored by clicking “Mode” and selecting the appropriate device configuration, as shown in Figure 2 in the case of the LMK04808B device.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Example: Using CodeLoader to Program the LMK04808B The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements with the LMK04808B device as an example. For more information on CodeLoader refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at http://www.national.com/timing/software/.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 3. Program/Load Device Assuming the Port Setup settings are correct, press the “Ctrl+L” shortcut or click “Keyboard Controls”  “Load Device” from the menu to program the device to the current state of the newly loaded LMK04800 file.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 5. Visual Confirmation of Frequency Lock After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2 are locked to the reference clock applied to CLKin1. This assumes LD_MUX = PLL1/2 DLD and LD_TYPE = Active High, which are the default settings. 6.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S complementary to each other, i.e.: Norm/Inv or Inv/Norm. 5. The phase noise may be measured with a spectrum analyzer or signal source analyzer. See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock outputs. National‟s Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies. See: http://www.national.com/timing/software/.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL Loop Filters and Loop Parameters In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL‟s purpose is to substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a “dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to minimize the impact of the reference clock phase noise.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL2 Loop Filter Table 5: PLL2 Loop Filter Parameters for LMK048xxB Integrated VCO PLL LMK04803B C1_A2 C2_A2 C3 (internal) C4 (internal) R2_A2 R3 (internal) R4 (internal) Charge Pump Current, K Phase Detector Frequency Frequency Kvco N Phase Margin Loop Bandwidth LMK04805B LMK04806B 0.047 3.9 0 0 0.62 0.2 0.2 LMK04808B nF nF nF nF kΩ kΩ kΩ 3.2 mA 122.88 MHz 1966.08 17.9 16 75 2211.84 16.5 18 75 2457.6 18.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Evaluation Board Inputs and Outputs The following table contains descriptions of the inputs and outputs for the evaluation board. Unless otherwise noted, the connectors described can be assumed to be populated by default. Additionally, some applicable CodeLoader programming controls are noted for convenience. Refer to the LMK04800 Family Datasheet for complete register programming information.
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L M K 0 4 8 X X Connector Name E V A L U A T I O N B O A R D Signal Type, Input/Output O P E R A T I N G I N S T R U C T I O N S Description Buffered outputs of OSCin port.
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L M K 0 4 8 X X E V A L U A T I O N Connector Name Signal Type, Input/Output Populated: J1 Power, Input Populated: VccVCO/Aux Power, Input Populated: VccVCXO/Aux Power, Input B O A R D O P E R A T I N G I N S T R U C T I O N S Description Alternative power supply input for the evaluation board using two unshielded wires (Vcc and GND). Apply power to either Vcc SMA or J1, but not both. Optional Vcc input to power the VCO circuit if separated voltage rails are needed.
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L M K 0 4 8 X X Connector Name E V A L U A T I O N B O A R D Signal Type, Input/Output O P E R A T I N G I N S T R U C T I O N S Description Reference Clock Inputs for PLL1 (CLKin0, 1). CLKin1 can alternatively be used as an External Feedback Clock Input (FBCLKin) in 0-delay mode or an RF Input (Fin) in External VCO mode. Reference Clock Inputs for PLL1 (CLKin0, 1) FBCLKin/CLKin1* is configured by default for a single-ended reference clock input from a 50-ohm source.
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L M K 0 4 8 X X Connector Name E V A L U A T I O N B O A R D Signal Type, Input/Output O P E R A T I N G I N S T R U C T I O N S Description Feedback VCXO clock input to PLL1 and Reference clock input to PLL2. By default, these SMAs are not connected to the traces going to the OSCin/OSCin* pins of the LMK048xxB. Instead, the single-ended output of the onboard VCXO (U2) drives the OSCin* input of the device and the OSCin input of the device is connected to GND with 0.1 uF.
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L M K 0 4 8 X X Connector Name E V A L U A T I O N B O A R D Signal Type, Input/Output O P E R A T I N G I N S T R U C T I O N S Description Programmable status output pin. By default, set to output the digital lock detect status signal for PLL1 and PLL2 combined. In the default CodeLoader modes, LED D5 will illuminate green when PLL lock is detected by the LMK048xxB (output is high) and turn off when lock is lost (output is low).
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L M K 0 4 8 X X Connector Name E V A L U A T I O N B O A R D Signal Type, Input/Output O P E R A T I N G I N S T R U C T I O N S Description Programmable status I/O pins. By default, set as input pins for controlling input clock switching of CLKin0 and CLKin1. These inputs will not be functional because CLKin_Select_MODE is set to 0 (CLKin0 Manual) by default in the Bits/Pins tab in CodeLoader.
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L M K 0 4 8 X X Connector Name E V A L U A T I O N B O A R D Signal Type, Input/Output O P E R A T I N G I N S T R U C T I O N S Description Programmable status I/O pin. By default, set as an input pin for synchronize the clock outputs with a fixed and known phase relationship between each clock output selected for SYNC. A SYNC event also causes the digital delay values to take effect.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Recommended Test Equipment Power Supply The Power Supply should be a low noise power supply, particularly when the devices on the board are being directly powered (onboard LDO regulators bypassed). Phase Noise / Spectrum Analyzer To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is recommended.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Programming 0-Delay Mode in CodeLoader Overview When enabling the 0-Delay mode the feedback path of the VCO is altered to include a clock output. See the datasheet for more details on 0-Delay functionality. The current version of the CodeLoader software does not include this extra divider in the frequency calculations when in holdover mode.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S by the reference input of PLL2 now. The PLL2 reference frequency will remain at the VCXO frequency. When the PLL1 VCXO frequency is different from the PLL2 reference frequency, a warning will be displayed on the clock outputs tab informing the user that PLL1 VCO and PLL2 reference frequency are mismatched and the one or more of the PLLs are out of lock.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Single Loop 0-Delay Mode Examples In Single Loop 0-Delay Mode, MODE = 8, the feedback from the VCO of PLL2 to the PLL2_P/PLL2 N divider is broken and a fed back clock output will drive the PLL2 N divider directly. This permits phase alignment between the clock output and the OSCin input (0-Delay). As such, the PLL2_N, PLL2_R, and PLL2_N_CAL divide values may need to be adjusted to permit the LMK04800 to lock.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Case 4 shows 0-Delay mode with CLKout divider not equal to the PLL2_P value; however the CLKout frequency will be less than the current phase detector frequency. This requires PLL2_R to be increased from a value of 1 to 2 to reduce the PLL2 phase detector frequency from 122.88 MHz to 61.44 MHz. Now the adjusted VCO frequency can be programmed to allow PLL2 to lock.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix A: CodeLoader Usage Code Loader is used to program the evaluation board with either an LPT port using the included CodeLoader cable or with a USB port using the optional USB-to-uWire cable available from http://store.national.com/. The part number is USB2UWIRE-IFACE.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs Tab Figure 9: Clock Outputs tab The Clock Outputs tab allows the user to control the output channel blocks, including: Clock Group Source from either VCO or OSCin (via OSC Mux1 and OSC Mux2) Channel Powerdown (affects digital and analog delay, clock divider, and buffer blocks) Digital Delay value and Half Step Clock Divide value Analog Delay value and Delay bypass/enable (per output) Clock Output for
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S values (shown in the PLL2 tab), and is given by: PLL2 N Total = VCO Divider * PLL2 N Prescaler * PLL2 N Counter Clicking on the cyan-colored PLL2 block that contains R, PDF and N values will bring the PLL2 tab into focus where these values may be modified, if needed. Clicking on the values in the box containing the Internal Loop Filter component (R3, C3, R4, C4) allow one to step through the possible values.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL1 Tab Figure 11: PLL1 tab The PLL1 tab allows the user to change the following parameters in Table 8. Table 8: Registers Controls and Descriptions in PLL1 tab Control Name Reference Oscillator Frequency (MHz) Phase Detector Frequency (MHz) Register Name n/a Description CLKin frequency of the selected reference clock. PLL1 Phase Detector Frequency (PDF).
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L M K 0 4 8 X X E V A L U A T I O N B O A R D VCO Frequency (MHz) n/a R Counter N Counter Phase Detector Polarity PLL1_R PLL1_N PLL1_CP_POL Charge Pump Gain PLL1_CP_GAIN Charge Pump State PLL1_CP_TRI O P E R A T I N G I N S T R U C T I O N S The VCO Frequency should be the OSCin frequency, except when operating in Dual PLL with 0-delay feedback. This value is calculated as: VCO Freq (OSCin freq) = PLL1 PDF * PLL1_N.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL2 Tab Figure 12: PLL2 tab The PLL2 tab allows the user to change the following parameters in Table 9.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D Phase Detector Polarity PLL2_CP_POL Charge Pump Gain PLL2_CP_GAIN Charge Pump State PLL2_CP_TRI O P E R A T I N G I N S T R U C T I O N S PLL2 Phase Detector Polarity. Click on the polarity sign to toggle polarity “+” or “–”. PLL2 Charge Pump Gain. Left-click/right-click to increase/decrease charge pump gain (100, 400, 1600, 3200 uA). PLL2 Charge Pump State. Click to toggle between Active and Tri-State.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Table 10: Register Controls and Descriptions on Bits/Pins tab Group Register Name RESET POWERDOWN MODE Mode Control PD_OSCin FEEDBACK_MUX OSCin_FREQ VCO_MUX uWire_LOCK CLKin_Select_MODE EN_CLKin1 CLKin EN_CLKin0 CLKinX_BUF_TYPE EN_LOS LOS_TIMEOUT IO Control Crystal EN_PLL2_XTAL XTAL_LVL LD_MUX LD_TYPE HOLDOVER_MUX Description Resets the device to default register values.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D DAC/Holdover IO Control – Sync HOLDOVER_TYPE Status_CLKin0 _MUX Status_CLKin0_TYPE Status_CLKin1_MUX Status_CLKin1_TYPE CLKin_Sel_INV O P E R A T I N G I N S T R U C T I O N S Sets I/O pin type on the Status_Holdover pin. Sets the selected signal on the Status_CLKin0 pin. Sets I/O pin type on the Status_CLKin0 pin. Sets the selected signal on the Status_CLKin1 pin. Sets I/O pin type on the Status_CLKin1 pin.
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L M K 0 4 8 X X E V A L U A T I O N HOLD_DLD_CNT DAC_CLK_DIV EN_MAN_DAC MAN_DAC DAC_LOW_TRIP DAC_HIGH_TRIP PLL1_WND_SIZE PLL1 PLL1_DLD_CNT CLKinX_PreR_DIV PLL1_N_DLY B O A R D O P E R A T I N G I N S T R U C T I O N S In HOLDOVER mode, wait for this many clocks of PLL1 PDF within the tolerances of PLL1_WND _SIZE before exiting holdover mode. DAC update clock is the PLL1 phase detector divided by this divisor. For proper operation, DAC update clock rate should be <= 100 kHz.
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L M K 0 4 8 X X E V A L U A T I O N PLL1_R_DLY PLL2_WND_SIZE PLL2_DLD_CNT PLL2 EN_PLL2_REF_2X PLL2_N_CAL PLL2_R3_LF PLL2_R4_LF PLL2_C3_LF PLL2_C4_LF PLL2_FAST_PDF Program Pins SYNC Status_CLKin0 Status_CLKin1 B O A R D O P E R A T I N G I N S T R U C T I O N S R delay causes clock outputs to lag clock input when in a 0-delay mode. Increasing the R delay value increases the output phase lag relative to the input.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Registers Tab Figure 14: Registers Tab The Registers tab shows the value of each register. This is convenient for programming the device to the desired settings, then exporting to a text file the register values in hexadecimal for use in your own application. By clicking in the “bit field” it is possible to manually change the value of registers by typing „1‟ and „0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix B: Typical Phase Noise Performance Plots PLL1 The LMK048xxB‟s dual PLL architecture achieves ultra low jitter and phase noise by allowing the external VCXO or Crystal‟s phase noise to dominate the final output phase noise at low offset frequencies and the internal VCO‟s phase noise to dominate the final output phase noise at high offset frequencies.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Phase Noise (dBc/Hz) VCXO Phase Noise -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 CVHD-950-122.88 10 100 1000 10000 100000 1000000 10000000 1E+08 Offset (Hz) Figure 15: Crystek CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz Table 12: VCXO Phase Noise at 122.88 MHz (dBc/Hz) Phase Offset Noise 10 Hz -76.6 100 Hz -108.9 1 kHz -137.4 10 kHz -153.3 100 kHz -162.0 1 MHz -165.7 10 MHz -168.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs (CLKout) The LMK04800 Family features programmable LVDS, LVPECL, and LVCMOS buffer modes for the CLKoutX and OSCout0 output pairs. The OSCout1 output pair has a LVPECL buffer. Included below are various phase noise measurements for each output format. LMK04808B CLKout Phase Noise Figure 16: LMK04808B CLKout Phase Noise Table 14: LMK04808B Phase Noise (dBc/Hz) Phase Noise and RMS Jitter (fs) 1474.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S For the LMK04808B, the internal VCO frequency is 2949.12 MHz. The divide-by-12 CLKout frequency is 245.76 MHz, and the divide-by-24 CLKout frequency is 122.88 MHz. Table 15: LMK04808B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies 245.76 245.76 245.76 122.88 122.88 122.88 Offset LVDS LVCMOS LVPECL LVDS LVCMOS LVPECL 100 Hz -103.7 -104.4 -106.1 -108.4 -110.4 -108.5 1 kHz -123.7 -125.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G LMK04808B OSCout Phase Noise Figure 17: LMK04808B OSCout Phase Noise Table 16: LMK04808B OSCout Phase Noise and RMS Jitter (fs) OSCout0 OSCout1 OSCin thru Offset LVPECL LVPECL CLKout -110.2 -111.1 -109.4 100 Hz -137.2 -136.1 -138.6 1 kHz -148.0 -148.0 -146.7 10 kHz -157.8 -156.0 -155.3 100 kHz -159.1 -159.4 -156.4 800 kHz -157.0 -157.5 -156.3 1 MHz -158.8 -159.2 -156.7 10 MHz -159.2 -159.5 -156.7 20 MHz RMS Jitter (fs) 94.1 91.0 123.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK04806B CLKout Phase Noise Figure 18: LMK04806B CLKout Phase Noise Table 17: LMK04806B Phase Noise (dBc/Hz) Phase Noise and RMS Jitter (fs) 1228.80 MHz 1228.80 MHz 491.52 MHz 491.52 MHz Offset LVDS LVPECL LVDS LVPECL -91.2 -90.5 -97.5 -98.2 100 Hz -111.2 -110.8 -118.7 -119.4 1 kHz -121.0 -121.1 -128.5 -128.6 10 kHz -121.3 -121.2 -129.5 -129.5 100 kHz -133.8 -133.7 -141.9 -141.9 800 kHz -135.8 -135.7 -143.4 -143.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Table 18: LMK04806B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies 245.76 245.76 245.76 122.88 122.88 122.88 Offset LVDS LVCMOS LVPECL LVDS LVCMOS LVPECL 100 Hz -105.8 -104.5 -106.5 -108.6 -113.0 -111.4 1 kHz -124.7 -124.9 -125.4 -130.2 -132.1 -131.0 10 kHz -134.8 -134.4 -134.9 -140.7 -140.7 -141.0 100 kHz -135.5 -135.4 -135.8 -141.7 -141.7 -141.9 800 kHz -147.8 -147.7 -148.0 -152.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G LMK04806B OSCout Phase Noise Figure 19: LMK04806B OSCout Phase Noise Table 19: LMK04806B OSCout Phase Noise and RMS Jitter (fs) OSCout0 OSCout1 OSCin thru Offset LVPECL LVPECL CLKout -110.3 -112.1 -110.0 100 Hz -136.9 -137.9 -138.9 1 kHz -151.1 -150.1 -150.0 10 kHz -154.3 -156.8 -154.6 100 kHz -158.9 -158.9 -156.6 800 kHz -159.2 -159.1 -156.6 1 MHz -159.4 -160.0 -156.8 10 MHz -157.6 -159.9 -156.9 20 MHz RMS Jitter (fs) 138.4 89.7 120.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK04803B CLKout Phase Noise Figure 20: LMK04803B CLKout Phase Noise Table 20: LMK04803B Phase Noise (dBc/Hz) Phase Noise and RMS Jitter (fs) 983.04 MHz 983.04 MHz 491.52 MHz 491.52 MHz Offset LVDS LVPECL LVDS LVPECL -93.0 -95.0 -99.7 -99.5 100 Hz -111.3 -113.1 -117.1 -118.3 1 kHz -121.8 -121.1 -126.9 -127.4 10 kHz -122.3 -121.9 -127.8 -128.3 100 kHz -134.9 -134.5 -140.3 -140.8 800 kHz -136.8 -136.3 -142.0 -142.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Table 21: LMK04803B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies 245.76 245.76 245.76 122.88 122.88 122.88 Offset LVDS LVCMOS LVPECL LVDS LVCMOS LVPECL 100 Hz -104.8 -104.2 -108.4 -112.1 -111.5 -112.7 1 kHz -124.8 -123.5 -125.0 -130.5 -130.2 -130.6 10 kHz -133.7 -134.0 -133.6 -140.1 -139.8 -140.1 100 kHz -134.4 -134.4 -134.6 -140.6 -140.4 -140.7 800 kHz -146.7 -146.7 -147.1 -152.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G LMK04803B OSCout Phase Noise Figure 21: LMK04803B OSCout Phase Noise Table 22: LMK04803B OSCout Phase Noise and RMS Jitter (fs) OSCout0 OSCout1 OSCin thru Offset LVPECL LVPECL CLKout -114.0 -113.1 -113.3 100 Hz -136.6 -137.2 -138.4 1 kHz -147.6 -146.6 -148.5 10 kHz -156.3 -156.2 -154.0 100 kHz -159.4 -159.2 -156.6 800 kHz -159.0 -159.3 -156.7 1 MHz -157.2 -158.7 -156.9 10 MHz -158.1 -159.4 -157.0 20 MHz RMS Jitter (fs) 107.1 92.4 119.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix C: Schematics Power Supplies 1 Vcc Vcc 2 Direct Power VccTP TESTPOINT J1 1 2 R330 DNP 1000 LDO Power Options 3 OUT DNP TAB ADJ 4 R338 240 B C318 1µF C319 0.1µF C325 1µF R336 C326 0.1µF C315 0.01µF DNPC316 0.1µF 1000 R343 DNPC333 DNP C322 0.1µF DNPC320 0.1µF C323 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK048xxB Device with Loop Filter and Crystal Circuits 1 2 3 4 5 6 Crystal-mode Loop Filter CLKout2 OSCin CPout1 48 C27 Vcc10_CLKout_CG3 45 uWire_CLK 44 uWire_LE 43 R60 DNP 0 uWire_DATA uWire_CLK C29 uWire_LE R306 DNP 0 Vcc9_PLL2 42 Y301 41 Vcc8_PDCP2 40 OSCout0_N 39 OSCout0_P 38 36 B 4.7k D1 SMV1249-074LF Vtune_XTAL R307 3 DNP 10k DNPC33 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Reference Inputs (CLKin0 & CLKin1), External VCXO (OSCin) & VCO Circuits, and OSCout1 Output 1 2 OSCin VCXO VCC_VCXO_TP Vcc_VCXO OSCin DNP SMA R18 FB 1000 ohm 600 mA C11 10µF A 3 4 R23 DNP 0 CLKin0* C1 C9 82pF 0 3 2 C368 100pF R21 DNPC8 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs (OSCout0, CLKout0 to CLKout3) 1 2 3 4 5 6 OSCout0 Default: LVDS, AC coupled VccCLKoutPlane R88 DNP 120 R89 DNP 82 R90 DNP 51 OSCout0 C44 A OSCout0_1_P OSCout0_P R91 0.1µF DNP 62 R231 240 GND R93 DNP 62 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs (CLKout4 to CLKout7) 1 2 3 CLKout4 A 4 CLKout5 Default: LVDS or LVCMOS, AC coupled VccCLKoutPlane R143 DNP 120 R144 DNP 82 C59 R141 DNP 51 R150 DNP 62 0.1µF R145 DNP 120 R151 CLKout6_P 33 R157 DNP 51 R234 CLKout6_N 33 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs (CLKout8 to CLKout11) 1 2 3 CLKout8 A 4 5 CLKout9 Default: LVDS or LVCMOS, AC coupled VccCLKoutPlane R185 DNP 120 Default: LVDS or LVCMOS, AC coupled A VccCLKoutPlane R186 DNP 82 R187 DNP 51 R188 DNP 120 CLKout8 C71 CLKout8_1_P CLKout8_P R191 DNP 240 6 R193 DNP 62 0.1µF R189 DNP 82 C72 R197 62DNP R195 R192 DNP 240 R194 DNP 62 GND R198 DNP 62 0.1µF 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S uWire Header, Logic I/O Ports and Status LEDs 1 2 3 4 CLKin Select 1 142-0711-201 uWire Header and Level Translation 142-0711-201 DNP A DNP TESTPOINT CLKuWire_TP R79 DNP 270 D2 D3 Red Red TESTPOINT R313 27k R317 TESTPOINT 15k R318 uWire_CLKin1_SEL TESTPOINT 15k DATAuWire_TP 15k R316 27k B TESTPOINT LEuWire_TP R321 uWire_LE 15k DNPC308 100pF Status_CLKin1 R322 27k Status_CLKin0 SYNC
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S USB Interface 1 2 3 4 5 6 A A VccAuxPlane R400 U_VCC3V3 0 USB_ID USB_SHIELD_GND U_VCC3V3 U_VCC3V3 R401 DNP 10k J400 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix D: Bill of Materials Table 23: Bill of Materials for LMK048xx Evaluation Boards Item Designator Description 1 C1, C5, C13, C20, FB, 120 ohm, 500 mA, 0603, RES, 0 ohm, 5%, 0.
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L M K 0 4 8 X X 5 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S C2, C12, C41, C302, C330, C346 C2pB2 C2_A1 C2_A2 C4, C69, C314, C322, C326, C367, C400, C401, C402, C409, C412, C414 CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603 Kemet C0603C104K4RACTU 6 CAP, CERM, 0.12uF, 50V, +/-10%, X7R, 0805 CAP, CERM, 0.68µF, 10V, +/-10%, X5R, 0603 CAP, CERM, 3900pF, 50V, +/-10%, X7R, 0603 CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603, CAP, CERM, 0.
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L M K 0 4 8 X X 25 26 27 28 29 C406, C407 C410, C411 C413, C415 Cb1_B1 CLKin0, CLKin0*, CLKout0, CLKout0*, CLKout2, CLKout2*, CLKout4, CLKout4*, CLKout6, CLKout6*, CLKout8, CLKout8*, CLKout10, CLKout10*, FBCLKin*/CLKin1*, OSCout0, OSCout0*, OSCout1, OSCout1* 30 31 32 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CAP, CERM, 18pF, 50V, +/-5%, C0G/NP0, 0603 CAP, CERM, 1uF, 16V, +/-10%, X5R, 0603 CAP, CERM, 0.01uF, 50V, +/-5%, X7R, 0603 CAP, CERM, 0.
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L M K 0 4 8 X X 41 42 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S R24 R26, R27, R83, R85 R43, R107, R108, R129, R130, R151, R152, R173, R174, R195, R196, R217, R218 RES, 18 ohm, 5%, 0.1W, 0603 RES, 270 ohm, 5%, 0.1W, 0603 Vishay-Dale Vishay-Dale CRCW060318R0JNEA CRCW0603270RJNEA 1 4 RES, 68 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060368R0JNEA 13 44 R61, R102, R117, R124, R138, R142, R158, R164, R182, R190, R206, R212, R228 RES, 51 ohm, 5%, 0.
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L M K 0 4 8 X X 61 U4, U300 62 U302 63 U303, U305 64 65 uWire Vcc 66 VccVCO/Aux, VccVCXO/Aux E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Precison Single Low Noise, Low 1/F corner Op Amp LMP7731MF 2 LP3878SD-ADJ 1 LP5900SD-3.3 2 52601-G10-8LF 142-0701-201 1 1 142-0711-201 2 Unpopulated Components ADT2-1T Balun MiniCircuits CAP, CERM, 2.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 76 C338, C344, C348, C354, C357, C365 CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603 Kemet C0603C104K3RACTU 0 77 C339, C345, C349, C355, C358, C366 CAP, CERM, 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 84 R1, R20, R23, R51, R52, R53, R54, R60, R63, R66, R69, R71, R72, R75, R76, R77, R78, R230, R300, R301, R305, R306, R308, R335, R339, R352, R363, R367, R370 RES, 0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06030000Z0EA 0 85 R5, R8, R14, R25, R33, R34, R41, R48, R64, R68, R90, R96, R99, R114, R121, R135, R141, R157, R163, R179, R187, R204, R209, R225, R376 RES, 51 ohm, 5%, 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 88 89 R28, R42, R65 R35, R44, R89, R95, R98, R101, R116, R118, R120, R123, R137, R140, R144, R146, R160, R162, R166, R168, R181, R184, R186, R189, R203, R205, R208, R211, R224, R227 RES, 100 ohm, 5%, 0.1W, 0603 RES, 82 ohm, 5%, 0.
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L M K 0 4 8 X X 96 97 98 99 100 101 102 R323 R326, R328, R330 R334 R360 R403, R406, R408, R409, R410 U3 U301 103 104 U400, Y400 Y300, Y301 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S RES, 2.2k ohm, 5%, 0.1W, 0603 FB, 1000 ohm, 600 mA, 0603 RES, 0 ohm, 5%, 0.125W, 0805 RES, 51k ohm, 5%, 0.1W, 0603 RES, 33 ohm, 5%, 0.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix E: PCB Layers Stackup 6-layer PCB Stackup includes: Top Layer for high-priority high-frequency signals (2 oz.) RO4003 Dielectric, 16 mils RF Ground plane (1 oz.) FR4, 4 mils Power plane #1 (1 oz.) FR4, 12.6 mils Ground plane (1 oz.) FR4, 8 mils Power Plane #2 (1 oz.) FR4, 12 mils Bottom Layer copper clad for thermal relief (2 oz.) Top Layer [LMK048xxENG.GTL] RO4003 (Er = 3.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix F: PCB Layout Layer #1 – Top 67
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Layer #2 – RF Ground Plane (Inverted) 68
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Layer #3 – Vcc Planes 69
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Layer #4 – Ground Plane (Inverted) 70
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Layer # 5 – Vcc Planes 2 71
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Layer #6 – Bottom 72
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Layers #1 and 6 – Top and Bottom (Composite) 73
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix G: Properly Configuring LPT Port When trying to solve any communications issue, it is most convenient to verify communication by programming the POWERDOWN bit to confirm normal or low supply current consumption of the evaluation board. LPT Driver Loading The parallel port must be configured for proper operation. To confirm that the LPT port driver is successfully loading click “LPT/USB”  “Check LPT.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Figure 23: Selecting the LPT Port Address Correct LPT Mode If communications are not working, then it is possible the LPT port mode is set improperly. It is recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS of the computer. Common terms for this desired parallel port mode are “Normal,” “Output,” or “AT.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix H: Troubleshooting Information If the evaluation board is not behaving as expected, the most likely issues are… 1) Board communication issue 2) Incorrect Programming of the device 3) Setup Error Refer to this checklist for a practical guide on identifying/exposing possible issues. 1) Confirm Communications Refer to Appendix G: Properly Configuring LPT Port to troubleshoot this item.
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L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 3) Confirm PLL2 operation/locking 1) Program LD_MUX = “PLL2_R/2” 2) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, examine PLL2_R programming. ii. If not, examine physical OSCin input. 3) Program LD_MUX = “PLL2_N/2” 4) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, confirm OSCin_FREQ is programmed to OSCin frequency. ii.
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