Datasheet

L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU099
45
7) If LD pin output is low, but the frequencies are the same, it is possible that excessive
leakage on Vtune pin is causing the digital lock detect to not activate. By default
PLL2 waits for the digital lock detect to go high before allowing PLL2 and the
integrated VCO to lock. Different VCXO models have different input leakage
specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1
charge pump current settings can cause the PLL1 charge pump to operate longer than
the digital lock detect timeout which allows the device to lock, but prevents the
digital lock detect from activating.
i. Redesign PLL1 loop filter with higher phase detector frequency
ii. Redesign PLL1 loop filter with higher charge pump current
iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp.
iv. Program RC_DLD1_Start = 0, this will allow PLL2 to starting lock even if
the digital lock detect on PLL1 is not high.
3) Confirm PLL2 operation/locking
1) Program PLL_MUX = “PLL 2 R Divider /2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, examine PLL2 register R programming.
ii. If not, examine physical OSCin input.
3) Program PLL_MUX = “PLL 2 N Divider /2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, confirm OSCin_FREQ is programmed to OSCin frequency.
ii. If not, examine PLL2 register N programming.
Naturally, the output frequency of the above two items should be the same frequency.
5) Program PLL_MUX = “PLL2 DLD Active High”
6) Confirm the LD pin output is high.
7) Program PLL_MUX = “PLL1/2 DLD Active High”
8) Confirm the LD pin output is high.