Datasheet

L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU099
9
Clock Outputs Tab
Figure 3 - Clock Outputs tab
The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock
mode (Bypass/Divided/Delayed/Divided & Delayed), set the clock output delay value (if delay is
enabled), and the clock output divider value (2, 4, 6, …, 510).
This tab also allows the user to select the VCO Divider value (2, 3, …, 8). Note that the total
PLL2 N divider value is composed of both the VCO Divider value and the N value shown in the
blue box in the image, and is given by: N_TOTAL = VCO Divider * N.
Clicking on the blue box that contains R, PDF and N values takes the user to the PLL2 tab where
these values may be changed.
Clicking on the components in the box containing the Internal Loop Filter values allows the user
to change these component values.