Datasheet
L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU099
44
Appendix J: Troubleshooting Information
If the evaluation board is not behaving as expected, the most likely issues are…
1) Board communication issue
2) Incorrect Programming of the device
3) Setup Error
Refer to this checklist for a practical guide on identifying/exposing possible issues.
1) Confirm Communications
Refer to Appendix I: Properly Configuring LPT Port to trouble shoot this item.
Remember to load device with Ctrl-L!
2) Confirm PLL1 operation/locking
1) Program PLL_MUX = “PLL 1 R Divider /2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine CLKin_SEL programming.
ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE.
iii. If not, examine PLL1 register R programming.
iv. If not, examine physical CLKin input.
3) Program PLL_MUX = “PLL 1 N Divider /2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine PLL1 register N programming.
ii. If not, examine physical OSCin input.
Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider
/2, on LD pin should be the same frequency.
5) Program PLL_MUX = “PLL1 DLD Active High”
6) Confirm the LD pin output is high.
i. If high, then PLL1 is locked, continue to PLL2 operation/locking.
(continued on next page)