Datasheet

November 2013 LMK040xx Evaluation Board User’s Guide SNAU045A 23
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
Figure 7. Typical Phase Noise, LMK040X1, VCXO Option (100 MHz). Jitter metrics are for an integration
bandwidth of 100 Hz to 20 MHz.
The following plot illustrates the phase noise performance of the LMK040XX using the VCXO option. In this case, the
VCXO is a Crystek CVPD-920-61.44 MHz LVPECL model.
Table 6. Test Conditions for Phase Noise Measurements, 61.44 VCXO option, LMK04020
Parameter
Value
PLL1 Reference clock input
CLKin0*, single-ended, CLKin0 AC-coupled to GND
PLL1 Reference Clock frequency
61.44 MHz
PLL1 Phase detector frequency
1024 MHz
PLL1 Charge Pump Gain
100 uA
VCXO frequency
61.44 MHz, Crystek CVPD-920
PLL2 phase detector frequency
61.44 MHz
PLL2 REF2X mode
disabled
PLL2 Charge Pump Gain
1600 uA
Typical Phase Noise, LMK040X1, VCXO Option
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
100 1000 10000 100000 1000000 10000000 100000000
Offset (Hz)
dBc
Fout, 1500 MHz, jitter = 193 fs
LVDS, 250 MHz, jitter = 215 fs
LVPECL, 250 MHz, jitter = 203 fs
LVCMOS, 250 MHz, jitter = 201 fs