Datasheet
24 SNAU075A LMK3806 Evaluation Board November 2013
Copyright © 2013, Texas Instruments Incorporated
Clock Outputs (CLKout)
The LMK03806 Family features programmable LVDS, LVPECL, and LVCMOS buffer modes for the
CLKoutX and OSCout0 output pairs. The OSCout1 output pair has a LVPECL buffer. Included below
are various phase noise measurements for each output format.
CLKoutPhaseNoise(div8anddiv16)
For the LMK03806B, the internal VCO frequency is 2400 MHz. The divide-by-8 CLKout frequency is
312.5 MHz, and the divide-by-16 CLKout frequency is 156.25 MHz.
Table 9: Typical Phase Noise Performance Plot Setup
Parameter Condition
LMK03806B Mode
100 MHz TCXO/XO Reference
Loop Filter Parameters As shown under “100 MHz Reference” in Table 3
CLKout for LVDS/LVCMOS CLKout8, with CLKout8* terminated in to 50
CLKout for LVPECL CLKout10, with CLKout10* terminated in to 50
Table 10: LMK03806B Phase Noise and RMS Jitter for Different CLKout Output Formats and
Frequencies
Offset
div8
LVPECL
div8
LVDS
div8
LVCMOS
div16
LVPECL
div16
LVDS
div16
LVCMOS
100 Hz
-91.9 -92.0 -93.2 -98.6 -98.8 -97.1
1 kHz
-113.8 -113.2 -113.4 -119.8 -119.3 -119.0
10 kHz
-122.6 -122.7 -122.5 -128.7 -128.4 -128.4
100 kHz
-128.7 -128.9 -128.4 -134.8 -134.9 -134.4
1 MHz
-148.1 -147.7 -148.2 -153.7 -153.0 -153.7
10 MHz
-157.6 -155.0 -157.2 -160.5 -158.0 -160.4
20 MHz
-157.7 -155.1 -157.2 -160.7 -158.1 -160.4
RMS Jitter (fs)
12 kHz to 20 MHz
141.1 144.0 143.2 145.3 155.4 149.8
RMS Jitter (fs)
100 Hz to 20 MHz
206.1 210.5 210.2 208.8 217.1 224.4