Datasheet

14 SNAU075A LMK3806 Evaluation Board November 2013
Copyright © 2013, Texas Instruments Incorporated
Connector Name
Signal Type,
Input/Output
Description
J1
Power,
Input
Alternative power supply input for the evaluation
board using two unshielded wires (Vcc and GND).
Apply power to either Vcc SMA or J1, but not both.
OSCin, OSCin*
Analog,
Input
By default, these SMAs are not connected to the
traces going to the OSCin/OSCin* pins of the
LMK03806B. Instead, the onboard crystal drives the
OSCin input of the device.
A single-ended or differential signal may be used to
drive the OSCin/OSCin* pins and must be AC
coupled. If operated in single-ended mode, the
unused input must be connected to GND with 0.1 uF.
Refer to the LMK03806 Datasheet section
“Electrical Characteristics” for PLL Reference Input
(OSCin) specifications.
uWire
CMOS,
Input/Output
10-pin header for uWire programming interface and
programmable logic I/O pins for the LMK03806B.
The uWire interface includes CLKuWire,
DATAuWire, and LEuWire signals.
The programmable logic I/O signals accessible
through this header include: SYNC. SYNC also has
a dedicated SMA and test point.
SYNC
CMOS,
Input/Output
Programmable status I/O pin. By default, set as an
input pin for synchronize the clock outputs with a
fixed and known phase relationship between each
clock output selected for SYNC.
In the default CodeLoader mode, SYNC will asserted
when the SYNC pin is low and the outputs to be
synchronized will be held in a logic low state. When
SYNC is unasserted, the clock outputs to be
synchronized are activated and will be initially phase
aligned with each other except for outputs
programmed with different digital delay values.
A SYNC event can also be programmed by toggling
the SYNC_POL_INV bit in the Bits/Pins tab in
CodeLoader.
Refer to the LMK03806 Datasheet section “Clock
Output Synchronization” for more information.