Datasheet

November 2013 LMK3806 Evaluation Board SNAU075A 11
Copyright © 2013, Texas Instruments Incorporated
See Typical Phase Noise Performance Plots for phase noise plots of the clock outputs. TI’s Clock Design
Tool can be used to calculate divider values to achieve desired clock output frequencies. See:
http://www.ti.com/tool/codeloader.
9. PLL Loop Filters and Loop Parameters
The default loop filter for the PLL has been configured for a 60 kHz bandwidth. The following table
contains the parameters for the PLL.
TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See:
http://www.ti.com/tool/codeloader.
PLL Loop Filter
Table 3: PLL Loop Filter Parameters for LMK03806B
 IntegratedVCOPLL
20 MHz Reference 100 MHz Reference
C1_LF
0.022 .022 nF
C2_LF
18 18 nF
C3 (internal)
0.01 0.01 nF
C4 (internal)
0.01 0.01 nF
R2_A2
0.82 0.82 k
R3 (internal)
0.2 0.2 k
R4 (internal)
0.2 0.2 k
Charge
Pump
Current, K
3.2 3.2 mA
Phase
Detector
Frequency
20 100 MHz
Frequency
2500 2400 MHz
Kvco
19 19 MHz/V
N
25 12
P
5 2
Phase
Margin
75 70 degrees
Loop
Bandwidth
63 60 kHz
Note: PLL Loop Bandwidth is a function of K, Kvco, N as well as loop components. Changing K and
N will change the loop bandwidth.