Datasheet

10 SNAU075A LMK3806 Evaluation Board November 2013

For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point.

This is important because when CodeLoader is closed, it remembers the last settings used for a particular

device. Again, remember to press Ctrl+L as the first step after loading a default mode.

7. Visual Confirmation of Frequency Lock

After a default mode is restored and loaded, LED D4, should illuminate red when the PLL is locked to the

reference crystal.

8. Enable Clock Outputs

While the LMK03806B offers programmable clock output buffer formats, the evaluation board is shipped

with preconfigured output terminations to match the default buffer type for each output. Refer to the

CLKout port description in the Evaluation Board Inputs and Outputs section.

To measure phase noise at one of the clock outputs, for example, CLKout0:

1. Click on the Clock Outputs tab,

2. Uncheck “Powerdown” in the Divider Powerdown box to enable the channel,

3. Set the following settings as needed:

a. Clock Divider value

b. Clock Output type.

4. Depending on the configured output type, the clock output SMAs can be interfaced to a test

instrument with a single-ended 50-ohm input as follows.

a. For LVDS:

i. A balun (like ADT2-1T) is recommended for differential-to-single-ended

conversion.

b. For LVPECL:

i. A balun can be used, or

ii. One side of the LVPECL signal can be terminated with a 50-ohm load and the

other side can be run single-ended to the instrument.

c. For LVCMOS:

i. There are two single-ended outputs, CLKoutX and

CLKoutX*, and each output can be set to Normal, Inverted,

or Off. There are nine (9) combinations of LVCMOS

modes in the Clock Output list.

ii. One side of the LVCMOS signal can be terminated with a

50-ohm load and the other side can be run single-

ended to the instrument.

iii. A balun may also be used. Ensure CLKoutX and CLKoutX* states are

complementary, i.e.: Norm/Inv or Inv/Norm.

5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.

Figure 6: Setting LVCMOS

Figure 5: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for

CLKout0