LMK03806 Evaluation Board User's Guide November 2013 SNAU075A
LMK03806 Ultra-low Jitter Clock Generator with 14 Outputs Evaluation Board Operating Instructions 2 SNAU075A LMK3806 Evaluation Board Copyright © 2013, Texas Instruments Incorporated November 2013
CONTENTS 1. INTRODUCTION ......................................................................................................... 5 2. QUICK START ............................................................................................................ 6 3. DEFAULT CODELOADER MODES FOR EVALUATION BOARDS ......................... 7 4. EXAMPLE: USING CODELOADER TO PROGRAM THE LMK03806B ................... 8 5. PROGRAM/LOAD DEVICE ...................................................................
LIST OF FIGURES Figure 1: Quick Start Diagram ...................................................................................................................................... 6 Figure 2: Selecting a Default Mode for the LMK03806B Device .................................................................................. 7 Figure 4: Loading the Device ........................................................................................................................................
1. Introduction The Texas Instruments LMK03806BEVAL evaluation module (EVM) helps designers evaluate the operation and performance of the LMK03806B high performance, ultra low-jitter, multirate clock generator. Texas Instruments CodeLoader software can be used to program the internal registers of the LMK03806B device through the USB2ANY-uWire interface. The CodeLoader software will run on a Windows 7 or Windows XP PC and can be downloaded from http://www.ti.
2. Quick Start 1. Connect a voltage of 5.0 volts to the Vcc SMA connector or terminal block. Device operates at 3.3 V using onboard LP3878-ADJ LDO. 2. Connect the uWire header via LPT or USB2ANY-uWire (See “EVM Software and Communication” Section for more information). 3. Program the device with CodeLoader. CodeLoader is available for download at: www.ti.com/tool/codeloader a. Select correct LMK03806B from “Select Device Clock Conditioners” Menu. b. Select a default mode from the “Mode” Menu.
3. Default CodeLoader Modes for Evaluation Boards CodeLoader saves the state of the selected LMK03806B device when exiting the software. To ensure a common starting point, the following modes listed in Table 2: Default CodeLoader Modes for LMK03806 may be restored by clicking “Mode” and selecting the appropriate device configuration, as shown in Figure 2 in the case of the LMK03806B device. Similar default modes are available for each LMK03806B device in CodeLoader.
4. Example: Using CodeLoader to Program the LMK03806B The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements with the LMK03806B device as an example. For more information on CodeLoader refer to CodeLoader Usage or the CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader. Before proceeding, be sure to follow the Quick Start section to ensure proper connections. 1.
5. Program/Load Device Assuming the Port Setup settings are correct, press the “Ctrl+L” shortcut or click “Keyboard Controls” “Load Device” from the menu to program the device to the current state of the newly loaded LMK03806 file. Figure 3: Loading the Device Once the device has been initially loaded, CodeLoader will automatically program changed registers so it is not necessary to re-load the device upon subsequent changes in the device configuration.
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point. This is important because when CodeLoader is closed, it remembers the last settings used for a particular device. Again, remember to press Ctrl+L as the first step after loading a default mode. 7. Visual Confirmation of Frequency Lock After a default mode is restored and loaded, LED D4, should illuminate red when the PLL is locked to the reference crystal. 8.
See Typical Phase Noise Performance Plots for phase noise plots of the clock outputs. TI’s Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies. See: http://www.ti.com/tool/codeloader. 9. PLL Loop Filters and Loop Parameters The default loop filter for the PLL has been configured for a 60 kHz bandwidth. The following table contains the parameters for the PLL. TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications.
10. Evaluation Board Inputs and Outputs The following table contains descriptions of the inputs and outputs for the evaluation board. Unless otherwise noted, the connectors described can be assumed to be populated by default. Additionally, some applicable CodeLoader programming controls are noted for convenience. Table 4: Evaluation Board Inputs and Outputs Connector Name Signal Type, Input/Output Description Clock outputs with programmable output buffers.
Connector Name Signal Type, Input/Output Description Buffered outputs of OSCin port. The output terminations on the evaluation board are shown below, the output type selected by default in CodeLoader is indicated by an asterisk (*): Default Board OSC output pair Termination OSCout0 LVPECL* (fixed) OSCout1 LVPECL* (fixed) OSCout0, OSCout0*, OSCout1, OSCout1* Analog, Output Only OSCout0 has a programmable LVDS, LVPECL, or LVCMOS output buffer.
Connector Name Signal Type, Input/Output J1 Power, Input Description Alternative power supply input for the evaluation board using two unshielded wires (Vcc and GND). Apply power to either Vcc SMA or J1, but not both. By default, these SMAs are not connected to the traces going to the OSCin/OSCin* pins of the LMK03806B. Instead, the onboard crystal drives the OSCin input of the device.
11. Recommended Test Equipment Power Supply The Power Supply should be a low noise power supply, particularly when the devices on the board are being directly powered (onboard LDO regulators bypassed). Phase Noise / Spectrum Analyzer To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is recommended. An Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the architecture of the E5052 is superior for phase noise measurements.
12. CodeLoader Usage Code Loader is used to program the evaluation board with either an LPT or USB2ANY-uWire interface available from http://www.ti.com. Port Setup Tab Figure 7: Port Setup Tab On the Port Setup tab, the user may select the type of communication port (LPT or USB) that will be used to program the device on the evaluation board. The Pin Configuration field is hardware dependent and normally does not need to be changed by the user. Figure 7: Port Setup Tab shows the default settings.
Clock Outputs Tab Figure 8: Clock Outputs Tab The Clock Outputs tab allows the user to control the output channel blocks, including: Clock Group Source from either Crystal or OSCin Channel Powerdown (affects clock divider, and buffer blocks) Clock Divide value Clock Output format (per output) Clicking on the cyan-colored PLL block that contains R, PDF and N values will bring the PLL tab into focus where these values may be modified, if needed.
Clicking on the values in the box containing the Internal Loop Filter component (R3, C3, R4, C4) allow one to step through the possible values. Left click to increase the component value, and right click to decrease the value. These values can also be changed in the Bits/Pins tab. The Reference Oscillator value field may be changed in either the Clock Outputs tab or the PLL tab. The PLL Reference frequency should match the frequency of the onboard Crystal.
Doubler EN_PLL_REF_2X R Counter N Counter OSCout Divider Phase Detector Polarity PLL_R PLL_N PLL_P PLL_CP_POL Charge Pump Gain PLL_CP_GAIN Charge Pump State PLL_CP_TRI PLL Doubler. 0 = Bypass Doubler 1 = Enable Doubler PLL R Counter value (1 to 4095). PLL N Counter value (1 to 49140). PLL N Prescaler value (2 to 8). PLL Phase Detector Polarity. Click on the polarity sign to toggle polarity “+” or “–”. PLL Charge Pump Gain.
Bits/Pins Tab Figure 10: Bits/Pins Tab The Bits/Pins tab allows the user to program bits directly, many of which are not available on other tabs. Brief descriptions for the controls on this tab are provided in Table 7: Register Controls and Descriptions on Bits/Pins Tab to supplement the datasheet. Refer to the LMK03806 Datasheet for more information.
Table 7: Register Controls and Descriptions on Bits/Pins Tab Mode Control Group IO Control – Sync Output Control Automatic Update Crystal Register Name RESET POWERDOWN uWire_LOCK OSCin_FREQ PLL_N_CAL EN_PLL_XTAL READBACK_TYPE LD_MUX LD_TYPE GPO0 GPO1 SYNC_TYPE SYNC_POL_INV SYNC_PLL_DLD NO_SYNC_CLKoutX_Y PLL_DLD_CNT PLL EN_PLL_REF_2X Program Pins PLL_R3_LF PLL_R4_LF PLL_C3_LF PLL_C4_LF SYNC TRIGGER November 2013 Description Resets the device to default register values.
Registers Tab Figure 11: Registers Tab The Registers tab shows the value of each register. This is convenient for programming the device to the desired settings, then exporting to a text file the register values in hexadecimal for use in your own application. By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’ and ‘0.
13. Typical Phase Noise Performance Plots PLL Figure 12: LMK03806B PLL VCO div2 LVPECL Phase Noise Table 8: LMK03806B PLL VCO div2 Phase Noise and RMS Jitter (fs) Offset 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz RMS Jitter (fs) 12 kHz to 20 MHz RMS Jitter (fs) 100 Hz to 20 MHz November 2013 Phase Noise (dBc/Hz) -98.3 -107.8 -106.6 -114.2 -136.6 -150.6 -151.
Clock Outputs (CLKout) The LMK03806 Family features programmable LVDS, LVPECL, and LVCMOS buffer modes for the CLKoutX and OSCout0 output pairs. The OSCout1 output pair has a LVPECL buffer. Included below are various phase noise measurements for each output format. CLKout Phase Noise (div8 and div16) For the LMK03806B, the internal VCO frequency is 2400 MHz. The divide-by-8 CLKout frequency is 312.5 MHz, and the divide-by-16 CLKout frequency is 156.25 MHz.
Figure 13: LMK03806B div8 CLKout LVPECL Phase Noise Figure 14: LMK03806B div8 CLKout LVDS Phase Noise November 2013 LMK3806 Evaluation Board Copyright © 2013, Texas Instruments Incorporated SNAU075A 25
Figure 15: LMK03806B div8 CLKout LVCMOS Phase Noise 26 SNAU075A LMK3806 Evaluation Board Copyright © 2013, Texas Instruments Incorporated November 2013
14. Schematics Power Supplies 1 2 3 4 5 6 Power Plane for LMK Except Outputs VccCore_TP TESTPOINT VccCore C41 0.1µF Vcc Core Supplies Vcc1-VCO, Vcc4-Digital, Vcc5-CLKin, Vcc6-PLL, Vcc7-OSCout0, and Vcc9-PLL2 A A R81 120 FB Direct Power VccTP Vcc Vcc R82 DNP 1000 1 TESTPOINT C42 0.1µF VccCore C43 10µF 2 3 4 5 142-0701-201 Vcc8_PDCP2 C44 1µF C45 0.
LMK03806B Device with Loop Filter and Crystal Circuits 1 2 D1 R1 DNP 270 3 4 5 R2 DNP 270 Red uWire Header and Level Translation D2 uWire Red Status3_TP Status2_TP TESTPOINT A TESTPOINT TESTPOINT Vcc13_CLKout_CG0 6 Vcc12_CLKout_CG5 R3 15k PLL Loop Filters Vcc11_CLKout_CG4 10 8 6 4 2 LEuWire_TP uWire_LE R4 27k DNPC1 100pF 9 7 5 3 1 HEADER_2X5 CLKout7_N CLKout6_P CLKout6* CLKout7_P CLKout6_N 49 50 51 CLKout7 CLKout7* Vcc11 CLKout8_N CLKout9_N CLKout8_P 52 53 CLKout8 5
Outputs, (OSCout0/1, CLKout0/1/2/3) 1 2 3 4 5 6 OSCout0 Default: LVDS, AC coupled OSCout1 Default: LVPECL, AC coupled R26 DNP 51 A OSCout0_1_P OSCout0_P R27 240 R25 DNP 51 OSCout1 C11 OSCout0 C12 OSCout1_1_P OSCout1_P SMA C13 240 0.1uF SMA A 0.1µF GND GND OSCout1* C14 OSCout0* C15 OSCout0_1_N OSCout0_N R28 240 OSCout1_1_N OSCout1_N SMA C16 240 0.1µF SMA 0.
Clock Outputs (CLKout 4/5/6/7) 1 A 2 3 CLKout4 4 R48 51 CLKout4 C25 CLKout4_1_P CLKout4_P R49 DNP 240 CLKout4_1_N R51 DNP 240 0.1µF CLKout5_1_P R52 DNP 240 R53 DNP 51 DNP 0.1µF SMA R54 51 GND CLKout6 Default: LVDS or LVCMOS, AC coupled DNP 51 CLKout6 C29 R57 CLKout6_2_P R58 DNP 240 CLKout6_1_P C30 CLKout7_N SMA 0.1µF R59 DNP 240 GND 0.
Clock Outputs (CLKout8/9/10/11) 1 A 2 3 CLKout8 6 R66 51 CLKout8 C33 CLKout8_1_P CLKout8_P A Default: LVDS or LVCMOS, AC coupled R65 DNP 51 C34 CLKout9_N SMA 0.1µF R68 DNP 240 GND 0.1µF CLKout9* CLKout9_1_N SMA DNP GND CLKout8* C35 CLKout8_1_N CLKout8_N R69 DNP 240 C36 CLKout9_P SMA 0.1µF R70 DNP 240 R71 DNP 51 GND B 5 CLKout9 Default: LVDS or LVCMOS, AC coupled R67 DNP 240 4 0.
Bill of Materials Table 11: Bill of Materials for LMK03806BEVAL Boards Item Description Qty 1 CAP, CERM, 47pF, 50V, +/5%, C0G/NP0, 0603 CAP, CERM, 3900pF, 50V, +/-10%, X7R, 0603 CAP, CERM, 0.
18 19 20 21 22 23 24 RES, 15k ohm, 5%, 0.1W, 0603 RES, 27k ohm, 5%, 0.1W, 0603 RES, 18 ohm, 5%, 0.1W, 0603 RES, 270 ohm, 5%, 0.1W, 0603 RES, 51 ohm, 5%, 0.1W, 0603 RES, 33 ohm, 5%, 0.
43 Connector, SMT, End launch SMA 50 Ohm 0 44 RES, 270 ohm, 5%, 0.1W, 0603 RES, 0 ohm, 5%, 0.1W, 0603 RES, 100 ohm, 5%, 0.1W, 0603 RES, 51 ohm, 5%, 0.1W, 0603 48 RES, 240 ohm, 5%, 0.1W, 0603 0 49 RES, 1.00k ohm, 1%, 0.
15. PCB Layers Stackup 6-layer PCB Stackup includes: Top Layer for high-priority high-frequency signals (2 oz.) FR4 Dielectric, 19 mils RF Ground plane (1 oz.) FR4, 14.5 mils Power plane (1 oz.) FR4, 19 mils Bottom Layer copper clad for thermal relief (2 oz.) Top Layer [LMK03806ENG.GTL] FR4 (Er = 4.8) 19 mil RF Ground plane [LMK03806ENG.G1] Power plane #1 [LMK03806ENG.G2] 61.3 mil thick FR4 (Er = 4.8) 14.5 mil FR4 19 mil Bottom Layer [LMK03806ENG.
16.
Figure 23: Layer 2 – RF Ground Plane November 2013 LMK3806 Evaluation Board Copyright © 2013, Texas Instruments Incorporated SNAU075A 37
Figure 24: Layer 3 – Vcc Planes 38 SNAU075A LMK3806 Evaluation Board Copyright © 2013, Texas Instruments Incorporated November 2013
Figure 25: Layer 4 - Bottom November 2013 LMK3806 Evaluation Board Copyright © 2013, Texas Instruments Incorporated SNAU075A 39
Figure 26: Top and Bottom (Composite) 40 SNAU075A LMK3806 Evaluation Board Copyright © 2013, Texas Instruments Incorporated November 2013
Appendix A: EVM Software and Communication: Interfacing uWire Codeloader is the software used to communicate with the EVM (Please download the latest version from TI.com http://www.ti.com/tool/codeloader). This EVM can be controlled through the uWire interface on board. There are two options in communicating with the uWire interface from the computer. OPTION 1 Open Codeloader.
The Adapter Board This table describes the pins configuration on the adapter board for each EVM board (See examples below table) Jumper Bank Code Loader Configuration EVM A B C D E F G H LMX2581 A4 B1 C2 E5 F1 G1 H1 BUFEN (pin 1), Trigger (pin 7) LMX2541 A4 C3 E4 F1 G1 H1 CE (pin 1), Trigger (pin 10) LMK0400x A0 C3 E5 F1 G1 H1 GOE (pin 7) LMK01000 A0 C1 E5 F1 G1 H1 GOE (pin 7) LMK030xx A0 C1 E5 F1 G1 H1 SYNC (pin 7) LMK02000 A0 C1 E5 F1 G1 H1 SYNC (pin 7) LMK0480x A0 B2 C3 E5 F0 G0 H1 Status_CLKin1 (pin 3)
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of EVMs for RF Products in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
