Datasheet

CPout
LEuWire
CLKuWire
DATAuWire
GOE
LD
(optional)
To Host
CLKout0
CLKout0*
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
CLKout4
CLKout4*
CLKout5
CLKout5*
CLKout6
CLKout6*
CLKout7
CLKout7*
To System
SYNC*
OSCin
OSCin*
Bias
Vcc
LDObyp1
LDObyp2
10 PF 0.1 PF
1 PF
0.1 PF
0.1 PF
LMK0300xx
100Ö
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013 www.ti.com
8 Application Information
8.1 SYSTEM LEVEL DIAGRAM
Figure 8-1. Typical Application
Figure 8-1 shows an LMK03000 family device used in a typical application. In this setup the clock may be
multiplied, reconditioned, and redistributed. Both the OSCin/OSCin* and CLKoutX/CLKoutX* pins can be
used in a single-ended or a differential fashion, which is discussed later in this datasheet. The GOE pin
needs to be high for the outputs to operate. One technique sometimes used is to take the output of the LD
(Lock Detect) pin and use this as an input to the GOE pin. If this is done, then the outputs will turn off if
lock detect circuit detects that the PLL is out of lock. The loop filter actually consists of seven components,
but four of these components that for the third and fourth poles of the loop filter are integrated in the chip.
The first and second pole of the loop filter are external.
8.2 BIAS PIN
See Section 6.1 for bias pin information.
8.3 LDO BYPASS
See Section 6.2 for LDO bypass information.
28 Application Information Copyright © 2006–2013, Texas Instruments Incorporated
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LMK03033C