Datasheet

LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013 www.ti.com
7.7.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
These bits set the output mode of the LD pin. The table below lists several different modes.
PLL_MUX[3:0] Output Type LD Pin Function
0 Hi-Z Disabled (default)
1 Push-Pull Logic High
2 Push-Pull Logic Low
3 Push-Pull Digital Lock Detect (Active High)
4 Push-Pull Digital Lock Detect (Active Low)
5 Push-Pull Analog Lock Detect
Open Drain
6 Analog Lock Detect
NMOS
Open Drain
7 Analog Lock Detect
PMOS
8 Invalid
9 Push-Pull N Divider Output/2 (50% Duty Cycle)
10 Invalid
11 Push-Pull R Divider Output/2 (50% Duty Cycle)
12 to 15 Invalid
7.7.3 POWERDOWN bit -- Device Power Down
This bit can power down the device. Enabling this bit powers down the entire device and all blocks,
regardless of the state of any of the other bits or pins.
POWERDOWN bit Mode
0 Normal Operation (default)
1 Entire Device Powered Down
7.7.4 EN_CLKout_Global bit -- Global Clock Output Enable
This bit overrides the individual CLKoutX_EN bits. When this bit is set to 0, all clock outputs are disabled,
regardless of the state of any of the other bits or pins.
EN_CLKout_Global bit Clock Outputs
0 All Off
1 Normal Operation (default)
7.7.5 EN_Fout bit -- Fout port enable
This bit enables the Fout pin.
EN_Fout bit Fout Pin Status
0 Disabled (default)
1 Enabled
26 General Programming Information Copyright © 2006–2013, Texas Instruments Incorporated
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LMK03033C