Datasheet

LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013 www.ti.com
7.3 REGISTER R8
The programming of register R8 provides optimum phase noise performance.
7.4 REGISTER R9
The programming of register R9 is optional. If it is not programmed the bit Vboost will be defaulted to 0,
which is the test condition for all electrical characteristics.
7.4.1 Vboost -- Voltage Boost
By enabling this bit, the voltage output levels for all clock outputs is increased. Also, the noise floor is
improved
Vboost Typical LVDS Voltage Output (mV) Typical LVPECL Voltage Output (mV)
0 350 810
1 390 865
7.5 REGISTER R11
This register only has one bit and only needs to be programmed in the case that the phase detector
frequency is greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to
the correct values.
7.5.1 DIV4 -- High Phase Detector Frequencies and Lock Detect
This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a
reliable output from the digital lock detect output in the case of a phase detector frequency frequency
greater than 20 MHz.
DIV4 Digital Lock Detect Circuitry Mode
Not divided
0
Phase Detector Frequency ≤ 20 MHz (default)
Divided by 4
1
Phase Detector Frequency > 20 MHz
7.6 REGISTER R13
7.6.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter Capacitors C3 and C4
These bits control the capacitor values for C3 and C4 in the internal loop filter.
Loop Filter Capacitors
VCO_C3_C4_LF[3:0] C3 (pF) C4 (pF)
0 0 (default) 10 (default)
1 0 60
2 50 10
3 0 110
4 50 110
5 100 110
6 0 160
7 50 160
8 100 10
9 100 60
10 150 110
11 150 60
12 to 15 Invalid
24 General Programming Information Copyright © 2006–2013, Texas Instruments Incorporated
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