Datasheet
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
www.ti.com
7.2 REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1
controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the
functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be from 0 to 7.
Table 7-2. Default Register Settings after Power on Reset
Default Bit
Bit Name Bit State Bit Description Register
Bit Value Location
RESET 0 No reset, normal operation Reset to power on defaults R0 31
CLKoutX_MUX 0 Bypassed CLKoutX mux mode 18:17
CLKoutX_EN 0 Disabled CLKoutX enable 16
R0 to R7
CLKoutX_DIV 1 Divide by 2 CLKoutX clock divide 15:8
CLKoutX_DLY 0 0 ps CLKoutX clock delay 7:4
Vboost 0 Normal Mode Output Power Control R9 16
DIV4 0 PDF ≤ 20 MHz Phase Detector Frequency R11 15
OSCin_FREQ 10 10 MHz OSCin OSCin Frequency in MHz 21:14
VCO_R4_LF 0 Low (~200 Ω) R4 internal loop filter values 13:11
R13
VCO_R3_LF 0 Low (~600 Ω) R3 internal loop filter values 10:8
VCO_C3_C4_LF 0 C3 = 0 pF, C4 = 10 pF C3 and C4 internal loop filter values 7:4
EN_Fout 0 Fout disabled Fout enable 28
EN_CLKout_Global 1 Normal - CLKouts normal Global clock output enable 27
POWERDOWN 0 Normal - Device active Device power down R14 26
PLL_MUX 0 Disabled Multiplexer control for LD pin 23:20
PLL_R 10 R divider = 10 PLL R divide value 19:8
PLL_CP_GAIN 0 100 µA Charge pump current 31:30
VCO_DIV 2 Divide by 2 VCO divide value R15 29:26
PLL_N 760 N divider = 760 PLL N divide value 25:8
7.2.1 RESET bit -- R0 only
This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting
this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this
bit. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if used with its
proper values and RESET = 0.
7.2.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock output. Changing between the different
modes changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode.
The different MUX modes and associated delays are listed below.
CLKoutX_MUX[1:0] Mode Added Delay Relative to Bypass Mode
0 Bypassed (default) 0 ps
1 Divided 100 ps
400 ps
2 Delayed
(In addition to the programmed delay)
500 ps
3 Divided and Delayed
(In addition to the programmed delay)
22 General Programming Information Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C