Datasheet

LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013 www.ti.com
1.2 DESCRIPTION
The LMK03000 family of precision clock conditioners combine the functions of jitter
cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a
Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.
The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO
Divider to feed the various clock distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a
programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple
integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking
devices in the same family.
1 FEATURES ............................................... 1 6.10 POWER ON RESET ............................... 17
1.1 TARGET APPLICATIONS ........................... 1 6.11 DIGITAL LOCK DETECT ........................... 18
1.2 DESCRIPTION ...................................... 2 7 General Programming Information ................ 19
2 Device Information ...................................... 3 7.1 RECOMMENDED PROGRAMMING SEQUENCE . 19
2.1 Functional Block Diagram ........................... 3 7.2 REGISTER R0 to R7 ............................... 22
2.2 Connection Diagram ................................. 4 7.3 REGISTER R8 ..................................... 24
3 Electrical Specifications ............................... 6 7.4 REGISTER R9 ...................................... 24
3.1 Absolute Maximum Ratings .......................... 6 7.5 REGISTER R11 .................................... 24
3.2 Recommended Operating Conditions ............... 6 7.6 REGISTER R13 .................................... 24
3.3 Package Thermal Resistance ....................... 6 7.7 REGISTER R14 .................................... 25
3.4 Electrical Characteristics ............................ 7 7.8 REGISTER R15 .................................... 27
3.5 Serial Data Timing Diagram ........................ 11 8 Application Information .............................. 28
4 Measurement Definitions ............................ 12 8.1 SYSTEM LEVEL DIAGRAM ........................ 28
4.1 Charge Pump Current Specification Definitions .... 12 8.2 BIAS PIN ........................................... 28
5 Typical Performance Characteristics ............. 13 8.3 LDO BYPASS ...................................... 28
6 Functional Description ............................... 15 8.4 LOOP FILTER ...................................... 29
8.5 CURRENT CONSUMPTION / POWER
6.1 BIAS PIN ........................................... 15
DISSIPATION CALCULATIONS ................... 30
6.2 LDO BYPASS ...................................... 15
8.6 THERMAL MANAGEMENT ........................ 31
6.3 OSCILLATOR INPUT PORT (OSCin, OSCin*) .... 15
8.7 TERMINATION AND USE OF CLOCK OUTPUTS
6.4 LOW NOISE, FULLY INTEGRATED VCO ......... 15
(DRIVERS) ......................................... 32
6.5 CLKout DELAYS ................................... 15
8.8 OSCin INPUT ...................................... 36
6.6 LVDS/LVPECL OUTPUTS ......................... 16
8.9 MORE THAN EIGHT OUTPUTS WITH AN
6.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION 16
LMK03000 FAMILY DEVICE ....................... 37
6.8 CLKout OUTPUT STATES ......................... 17
Revision History ............................................ 38
6.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT 17
2 Contents Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C