Datasheet

Phase Error < g

Phase Error < g Phase Error < g Phase Error < g

Phase Error > *

YES

NONONO

NONO

YES YES

YES YES YES

Phase Error < g

START

Lock Detected =

False

Lock Detected =

True

LMK03000, LMK03000C, LMK03000D, LMK03001

LMK03001C, LMK03001D, LMK03033, LMK03033C

SNAS381O –NOVEMBER 2006–REVISED MARCH 2013

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6.11 DIGITAL LOCK DETECT

The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase

detector to a RC generated delay of ε. To indicate a locked state the phase error must be less than the ε

RC delay for 5 consecutive reference cycles. Once in lock, the RC delay is changed to approximately δ.

To indicate an out of lock state, the phase error must become greater δ. The values of ε and δ are shown

in the table below:

ε δ

10 ns 20 ns

To utilize the digital lock detect feature, PLL_MUX must be programmed for "Digital Lock Detect (Active

High)" or "Digital Lock Detect (Active Low)." When one of these modes is programmed the state of the LD

pin will be set high or low as determined by the description above as shown in Figure 6-2.

When the device is in power down mode and the LD pin is programmed for a digital lock detect function,

LD will show a "no lock detected" condition which is low or high given active high or active low circuitry

respectively.

The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4

word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to

divide the comparison frequency presented to the lock detect circuit by 4.

Figure 6-2. Digital Lock Detect Flowchart

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