Datasheet

LMK03000, LMK03000C, LMK03000D, LMK03001

LMK03001C, LMK03001D, LMK03033, LMK03033C

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SNAS381O –NOVEMBER 2006–REVISED MARCH 2013

6.8 CLKout OUTPUT STATES

Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable

control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit

(EN_CLKout_Global).

All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or

EN_CLKout_Global is set to 0.

CLKoutX_EN bit EN_CLKout_Global bit GOE pin CLKoutX Output State

1 1 Low Low

Don't care 0 Don't care Off

0 Don't care Don't care Off

1 1 High / No Connect Enabled

When an LVDS output is in the Off state, the outputs are at a voltage of approximately 1.5 volts. When an

LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt.

6.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT

The GOE pin provides an internal pull-up resistor as shown on the functional block diagram. If it is not

terminated externally, the clock output states are determined by the Clock Output Enable bits

(CLKoutX_EN) and the EN_CLKout_Global bit.

By programming the PLL_MUX register to Digital Lock Detect Active High, the Lock Detect (LD) pin can

be connected to the GOE pin in which case all outputs are set low automatically if the synthesizer is not

locked.

6.10 POWER ON RESET

When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit

sets all registers to their default values, see the Section 7 section for more information on default register

values. Voltage should be applied to all Vcc pins simultaneously.

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