Datasheet

Distribution

Path

SYNC*

CLKout0

CLKout1

CLKout2

LMK03000, LMK03000C, LMK03000D, LMK03001

LMK03001C, LMK03001D, LMK03033, LMK03033C

SNAS381O –NOVEMBER 2006–REVISED MARCH 2013

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6.6 LVDS/LVPECL OUTPUTS

By default all the clock outputs are disabled until programmed.

Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the

outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global

to 0.

The duty cycle of the LVDS and LVPECL clock outputs are shown in the table below.

VCO_DIV CLKoutX_MUX Duty Cycle

Any Divided, or Divided and Delayed 50%

2, 4, 6, 8 Any 50%

3 Bypassed, or Delayed 33%

5 Bypassed, or Delayed 40%

7 Bypassed, or Delayed 43%

6.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION

The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the

divided outputs are also held in a logic low state. The bypassed outputs will continue to operate normally.

Shortly after the SYNC* pin goes high, the divided clock outputs are activated and will all transition to a

high state simultaneously. All the outputs, divided and bypassed, will now be synchronized. Clocks in the

bypassed state are not affected by SYNC* and are always synchronized with the divided outputs.

The SYNC* pin must be held low for greater than one clock cycle of the output of the VCO Divider, also

known as the distribution path. Once this low event has been registered, the outputs will not reflect the low

state for four more cycles. This means that the outputs will be low on the fifth rising edge of the

distribution path. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously

transition high until four more distribution path clock cycles have passed, which is the fifth rising edge of

the distribution path. See the timing diagram in Figure 6-1 for further detail. The clocks are programmed

as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided,

and CLKout2_DIV = 4. To synchronize the outputs, after the low SYNC* event has been registered, it is

not required to wait for the outputs to go low before SYNC* is set high.

Figure 6-1. SYNC* Timing Diagram

The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the

SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not

used, clock output synchronization is not ensured.

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