Datasheet

LMK03000, LMK03000C, LMK03000D, LMK03001

LMK03001C, LMK03001D, LMK03033, LMK03033C

www.ti.com

SNAS381O –NOVEMBER 2006–REVISED MARCH 2013

6 Functional Description

The LMK03000 family of precision clock conditioners combine the functions of jitter

cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a

Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially

integrated loop filter, three LVDS, and five LVPECL clock output distribution blocks.

The devices include internal 3rd and 4th order poles to simplify loop filter design and improve spurious

performance. The 1st and 2nd order poles are off-chip to provide flexibility for the design of various loop

filter bandwidths.

The LMK03000 family has multiple options for VCO frequencies. The VCO output is optionally accessible

on the Fout port. Internally, the VCO output goes through an VCO Divider to feed the various clock

distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a

programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple

integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking

devices in the same family.

6.1 BIAS PIN

To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This

is important for low noise performance.

6.2 LDO BYPASS

To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a

0.1 µF capacitor.

6.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)

The purpose of OSCin is to provide the PLL with a reference signal. Due to an internal DC bias the OSCin

port should be AC coupled, refer to the Section 8.1 in the Section 8 section. The OSCin port may be

driven single-endedly by AC grounding OSCin* with a 0.1 µF capacitor.

6.4 LOW NOISE, FULLY INTEGRATED VCO

The LMK03000 family of devices contain a fully integrated VCO. In order for proper operation the VCO

uses a frequency calibration algorithm. The frequency calibration algorithm is activated any time that the

R15 register is programmed. Once R15 is programmed the temperature may not drift more than the

maximum allowable drift for continuous lock, ΔT

, or else the VCO is not ensured to stay in lock.

For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15

is programmed.

6.5 CLKout DELAYS

Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY)

support a 150 ps step size and range from 0 to 2250 ps of total delay.

Submit Documentation Feedback

Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033

LMK03033C