Datasheet
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O –NOVEMBER 2006–REVISED MARCH 2013
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Electrical Characteristics
(1)
(continued)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T
A
≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values
represent most likely parametric norms at Vcc = 3.3 V, T
A
= 25 °C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured).
Symbol Parameter Conditions Min Typ Max Units
Clock Distribution Section
(1) (2)
- LVDS Clock Outputs
CLKoutX_MUX
= Bypass (no 20
R
L
= 100 Ω
divide or delay)
Distribution Path =
CLKoutX_MUX
Jitter
ADD
Additive RMS Jitter
(1)
765 MHz fs
= Divided (no
Bandwidth =
delay) 75
12 kHz to 20 MHz
CLKoutX_DIV
= 4
Equal loading and identical clock
t
SKEW
CLKoutX to CLKoutY
(3)
configuration -30 ±4 30 ps
R
L
= 100 Ω
V
OD
Differential Output Voltage R
L
= 100 Ω 250 350 450 mV
Change in magnitude of V
OD
for
ΔV
OD
R
L
= 100 Ω -50 50 mV
complementary output states
V
OS
Output Offset Voltage R
L
= 100 Ω 1.070 1.25 1.370 V
Change in magnitude of V
OS
for
ΔV
OS
R
L
= 100 Ω -35 35 mV
complementary output states
I
SA
Clock Output Short Circuit Current
Single-ended outputs shorted to GND -24 24 mA
I
SB
single-ended
Clock Output Short Circuit Current
I
SAB
Complementary outputs tied together -12 12 mA
differential
Clock Distribution Section
(1) (2)
- LVPECL Clock Outputs
CLKoutX_MUX
= Bypass (no 20
R
L
= 100 Ω
divide or delay)
Distribution Path =
CLKoutX_MUX
Jitter
ADD
Additive RMS Jitter
(1)
765 MHz fs
= Divided (no
Bandwidth =
delay) 75
12 kHz to 20 MHz
CLKoutX_DIV
= 4
Equal loading and identical clock
t
SKEW
CLKoutX to CLKoutY
(3)
configuration -30 ±3 30 ps
Termination = 50 Ω to Vcc - 2 V
Vcc -
V
OH
Output High Voltage V
0.98
Termination = 50 Ω to Vcc - 2 V
Vcc -
V
OL
Output Low Voltage V
1.8
V
OD
Differential Output Voltage R
L
= 100 Ω 660 810 965 mV
Digital LVTTL Interfaces
(4)
V
IH
High-Level Input Voltage 2.0 Vcc V
V
IL
Low-Level Input Voltage 0.8 V
I
IH
High-Level Input Current V
IH
= Vcc -5.0 5.0 µA
I
IL
Low-Level Input Current V
IL
= 0 -40.0 5.0 µA
Vcc -
V
OH
High-Level Output Voltage I
OH
= +500 µA V
0.4
V
OL
Low-Level Output Voltage I
OL
= -500 µA 0.4 V
(1) The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications
apply to the clock distribution section only and this adds in an RMS fashion to the shaped jitter of the PLL and the VCO.
(2) For CLKout frequencies above 1 GHz, the delay should be limited to one half of a period. For 1 GHz and below, the maximum delay can
be used.
(3) Specification is ensured by characterization and is not tested in production.
(4) Applies to GOE, LD, and SYNC*.
10 Electrical Specifications Copyright © 2006–2013, Texas Instruments Incorporated
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