Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

LMK0300xx

Precision Clock

Conditioner

Recovered

³GLUW\´FORFNRU

clean clock

0XOWLSOH³FOHDQ´FORFNVDW

different frequencies

Fout

CLKout7

CLKout4

CLKout1

CLKout0

DAC

Serializer/

Deserializer

LMX2531

PLL+VCO

ADC

> 1 Gsps

FPGA

OSCin

LMK03000, LMK03000C, LMK03000D, LMK03001

LMK03001C, LMK03001D, LMK03033, LMK03033C

www.ti.com

SNAS381O –NOVEMBER 2006–REVISED MARCH 2013

LMK03000 Family Precision Clock Conditioner with Integrated VCO

Check for Samples: LMK03000, LMK03000C, LMK03000D, LMK03001, LMK03001C, LMK03001D, LMK03033, LMK03033C

1 FEATURES

• Integrated VCO with Very Low Phase Noise • Partially Integrated Loop Filter

Floor

• Dedicated Divider and Delay Blocks on Each

• Integrated Integer-N PLL with Outstanding Clock Output

Normalized Phase Noise Contribution of -224

• Pin Compatible Family of Clocking Devices

dBc/Hz

• 3.15 to 3.45 V Operation

• VCO Divider Values of 2 to 8 (All Divides)

• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)

• Channel Divider Values of 1, 2 to 510 (even

• 200 fs RMS Clock Generator Performance (10

divides)

Hz to 20 MHz) with a Clean Input Clock

• LVDS and LVPECL Clock Outputs

1.1 TARGET APPLICATIONS

VCO

• Data Converter Clocking

Device Outputs

Tuning Range RMS Jitter

• Networking, SONET/SDH, DSLAM

(MHz) (fs)

• Wireless Infrastructure

LMK03000C 400

• Medical

LMK03000 1185 - 1296 800

• Test and Measurement

LMK03000D 1200

3 LVDS

5 LVPECL

• Military / Aerospace

LMK03001C 400

LMK03001 1470 - 1570 800

LMK03001D 1200

LMK03033C 500

4 LVDS

1843 - 2160

4 LVPECL

LMK03033 800

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (45 pages)

PAGE 1
LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 1.2 www.ti.com DESCRIPTION The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock.
PAGE 3
LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 2 Device Information Functional Block Diagram CPout 2.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 CLKout7* CLKout7 Vcc14 CLKout6* CLKout6 Vcc13 CLKout5* CLKout5 Vcc12 CLKout4* CLKout4 Vcc11 Connection Diagram 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 Bias Fout 2 35 NC Vcc1 3 34 NC CLKuWire 4 33 Vcc10 DATAuWire 5 32 CPout LEuWire 6 31 Vcc9 NC 7 30 Vcc8 Vcc2 8 29 OSCin* LDObyp1 9 28 OSCin LDObyp2 10 27 SYNC* 26
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 Table 2-1.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 3 Electrical Specifications 3.1 Absolute Maximum Ratings (1) (2) (3) Symbol Ratings Units Power Supply Voltage Parameter VCC -0.3 to 3.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 3.4 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 Electrical Characteristics (1) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured).
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured).
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured).
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured).
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 Electrical Characteristics (1) (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured).
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com 4 Measurement Definitions 4.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 5 Typical Performance Characteristics NOTE 1000 1000 900 900 800 800 700 700 600 Vboost = 1 500 400 VOD (mV) VOD (mV) These plots show performance at frequencies beyond what the part is ensured to operate at to give the user an idea of the capabilities of the part, but they do not imply any sort of ensured specification.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com -135 -140 Delay = 2250 ps Delay=1800 ps NOISE FLOOR (dBc/Hz) Delay = 900 ps -145 -150 -155 Delay = 450 ps -160 Delay = 0 ps -165 -170 10 100 1000 FREQUENCY (MHz) To estimate this noise, only the output frequency is required. Divide value and input frequency are not integral.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 6 Functional Description The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 6.6 www.ti.com LVDS/LVPECL OUTPUTS By default all the clock outputs are disabled until programmed. Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 6.8 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 CLKout OUTPUT STATES Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global).
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com 6.11 DIGITAL LOCK DETECT The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector to a RC generated delay of ε. To indicate a locked state the phase error must be less than the ε RC delay for 5 consecutive reference cycles. Once in lock, the RC delay is changed to approximately δ.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 7 General Programming Information The LMK03000 family of devices are programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0].
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com Register Table 7-1.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 7.2 www.ti.com REGISTER R0 to R7 Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of these bits are identical.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 7.2.3 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 CLKoutX_DIV[7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are aligned.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 7.3 www.ti.com REGISTER R8 The programming of register R8 provides optimum phase noise performance. 7.4 REGISTER R9 The programming of register R9 is optional. If it is not programmed the bit Vboost will be defaulted to 0, which is the test condition for all electrical characteristics. 7.4.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 7.6.2 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 VCO_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 These bits control the R3 resistor value in the internal loop filter. The recommended setting for VCO_R3_LF[2:0] = 0 for optimum phase noise and jitter. 7.6.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 7.7.2 www.ti.com PLL_MUX[3:0] -- Multiplexer Control for LD Pin These bits set the output mode of the LD pin. The table below lists several different modes.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 7.8 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 REGISTER R15 Programming R15 also activates the frequency calibration routine. 7.8.1 PLL_N[17:0] -- PLL N Divider These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and precedes the PLL phase detector.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com 8 Application Information 8.1 SYSTEM LEVEL DIAGRAM Vcc Bias CPout 1 PF 0.1 PF OSCin CLKout0 CLKout0* 100Ö CLKout1 CLKout1* OSCin* 0.1 PF CLKout2 CLKout2* LEuWire CLKuWire CLKout3 CLKout3* DATAuWire CLKout4 To Host SYNC* CLKout4* LMK0300xx LD (optional) GOE To System CLKout5 CLKout5* CLKout6 CLKout6* LDObyp1 LDObyp2 10 PF CLKout7 CLKout7* 0.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 8.4 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 LOOP FILTER LMK0300xx R3 Phase Detector R4 C3 C4 Internal Loop Filter C2 C1 External Loop Filter R2 Figure 8-2. Loop Filter The internal charge pump is directly connected to the integrated loop filter components. The first and second pole of the loop filter are externally attached as shown in Figure 8-2.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 8.5 www.ti.com CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following table serves to provide enough information to allow the user to calculate estimated current consumption of the device. Unless otherwise noted Vcc = 3.3 V, TA = 25 °C. Table 8-1. Block Current Consumption Current Consumption at 3.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 8.6 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 THERMAL MANAGEMENT Power consumption of the LMK03000 family of devices can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 8.7 www.ti.com TERMINATION AND USE OF CLOCK OUTPUTS (DRIVERS) When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance: • Transmission line theory should be followed for good impedance matching to prevent reflections. • Clock drivers should be presented with the proper loads.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcc - 2 V as shown in Figure 8-5. Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) as shown in Figure 8-6 for Vcc = 3.3 V.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 8.7.2 www.ti.com Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 8.7.3 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal. It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 8.7.4 www.ti.com Conversion to LVCMOS Outputs To drive an LVCMOS input with an LMK03000 family LVDS or LVPECL output, an LVPECL/LVDS to LVCMOS converter such as TI's DS90LV018A, DS90LV028A, DS90LV048A, etc. is required. For best noise performance, LVPECL provides a higher voltage swing into input of the converter. 8.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C www.ti.com 8.9 SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 MORE THAN EIGHT OUTPUTS WITH AN LMK03000 FAMILY DEVICE The LMK03000 family devices include eight or less outputs. When more than 8 outputs are required the footprint compatible LMK01000 family may be used for clock distribution.
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LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK03033C SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (March 2013) to Revision O • 38 Changed layout of National Data Sheet to TI format Application Information Page ..........................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMK03000CISQ/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03000CISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03000DISQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMK03033ISQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 LMK03033ISQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK03033CISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK03033CISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 LMK03033ISQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMK03033ISQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMK03033ISQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.
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