Datasheet

SNAU118

LMK01801BEVAL Evaluation Board Operating Instructions

General Description

The LMK01801 Evaluation Board simplifies evaluation of the LMK01801 Dual Clock Buffer

Divider. Configuring and controlling the board is accomplished using Texas Instrument’s

CodeLoader software, which can be downloaded from: http://www.ti.com/tool/codeloader

. The

LMK01801 can also be configured to operate in a pin control mode via headers on the PCB.

Block Diagram

The block diagram in Figure 1 illustrates the functional architecture of the LMK01801 clock

divider buffer. The LMK01801 is a very low noise solution for clocking systems that require

distribution and frequency division of precision clocks. The LMK01801 features extremely low

residual noise, frequency division, digital and analog delay adjustments, and fourteen (14)

programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential

output). The LMK01801 features two independent inputs that can be driven differentially or in

single-ended mode. The first input drives output Bank A consisting of eight (8) outputs. The

second input drives output Bank B consisting of six (6) outputs.

Figure 1 - LMK01801 Block Diagram