Datasheet

SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
11
5. Enable Clock Outputs
To measure phase noise at the clock outputs,
1. Click on the “Bank A” tab,
2. Enable an output,
3. Then set the
a. CLKout Type,
b. divide value
Figure 7 - Setting Divide, CLKout_TYPE, Enabled for CLKout1 on "Clock Outputs" tab.
4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer.
a. For LVDS, a balun is recommended such as the ADT2-1T (for frequency range of
0.4 MHz to 450 MHz).
b. For LVPECL,
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50 ohm load and
the other side can be run to the test equipment
single ended.
c. For LVCMOS,
i. One side of the LVCMOS signal can be
terminated with a 50 ohm load and the other
side can be run to the test equipment single
ended.
5. The phase noise may be measured with a spectrum analyzer
or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
Figure 8 - Setting
LVCMOS modes.
This CLKoutX frequency value is only valid if
the correct clock in value is specified. It may
not necessarily represent the actual frequency
unless manually entered. This is a
mathematical calculation only, not a measured
value.