SNAU118 LMK01801 Dual Clock Divider Buffer Evaluation Board Operating Instructions 7 December 2011 LMK01801 EVAL Texas Instruments, Inc.
SNAU118 Table of Contents TABLE OF CONTENTS ....................................................................................................................... 2 TABLE OF FIGURES........................................................................................................................... 3 GENERAL DESCRIPTION ................................................................................................................... 4 Block Diagram ...................................................
SNAU118 Table of Figures Figure 1 - LMK01801 Block Diagram ........................................................................................... 4 Figure 2 - Quick Start Diagram ...................................................................................................... 6 Figure 3 - Pin Control Mode Quick Start Diagram......................................................................... 7 Figure 4 – Selecting the LMK01801 .................................................................
SNAU118 General Description The LMK01801 Evaluation Board simplifies evaluation of the LMK01801 Dual Clock Buffer Divider. Configuring and controlling the board is accomplished using Texas Instrument’s CodeLoader software, which can be downloaded from: http://www.ti.com/tool/codeloader. The LMK01801 can also be configured to operate in a pin control mode via headers on the PCB. Block Diagram The block diagram in Figure 1 illustrates the functional architecture of the LMK01801 clock divider buffer.
SNAU118 Evaluation Board Kit Contents The evaluation board kit contains… An LMK01801 Evaluation board. LMK01801 Family quick start guide. o Evaluation board instructions are downloadable from the product folder on Texas Instument’s website, www.ti.com/. CodeLoader uWire cable (LPT --> uWire). A USB interface board can be purchased separately under NSID USB2UWIRE_IFACE. The CodeLoader software will run on a Windows 2000 or Windows XP PC.
SNAU118 Quick Start – Code Loader Mode 1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate terminal block. 2. Connect a reference clock from a signal generator or other source. Exact frequency depends on programming. 3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A USB communication option is available, search at www.ti.com/ for: USB2UWIREIFACE. 4.
SNAU118 Quick Start – Pin Control Mode 1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector. 2. Connect a reference clock from a signal generator or other source. Exact frequency depends on programming. 3. Install a jumper on EN_PIN_CTRL header in either the High or Low position. 4. Install other jumpers on Type0, Type1, Type2, DivVal0, DivVal1, and DivVal2 headers based on the configurations shown in Table 1 and Table 2.
SNAU118 Pin Control Modes For the following tables, Low is defined as installing a jumper between pins 5 and 6 on the desired header. A HIGH is defined as installing a jumper between pins 1 and 2 on the desired header.
SNAU118 Using CodeLoader to Program the LMK01801 The purpose of this section is to walk the user through using CodeLoader to make some measurements with the LMK01801 device. For more information on CodeLoader refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader/. Before proceeding, be sure to follow the Quick Start section above to ensure proper connections. 1.
SNAU118 3. Program/Load Device Press “Ctrl – L” Assuming the Port Settings are correct, it is now possible to click “Keyboard Controls” “Load Device” from the menu to program the device to the current state of the newly loaded LMK01801 file. CtrlL is the accelerator assigned to the Load Device option and is very convenient.
SNAU118 5. Enable Clock Outputs This CLKoutX frequency value is only valid if the correct clock in value is specified. It may not necessarily represent the actual frequency unless manually entered. This is a mathematical calculation only, not a measured value. To measure phase noise at the clock outputs, 1. Click on the “Bank A” tab, 2. Enable an output, 3. Then set the a. CLKout Type, b. divide value Figure 7 - Setting Divide, CLKout_TYPE, Enabled for CLKout1 on "Clock Outputs" tab. 4.
SNAU118 Evaluation Board Inputs/Outputs The following table contains descriptions of the various inputs and outputs for the evaluation board. Table 3. LMK01801 Evaluation Board I/O Connector Name CLKout0 / CLKout0*, CLKout2 / CLKout2*, CLKout4 / CLKout4*, CLKout6 / CLKout6*, CLKout8 / CLKout8*, CLKout9/ CLKout9*, CLKout10 / CLKout10*, CLKout11/ CLKout11*, CLKout12 / CLKout12*, CLKout13 / CLKout13* Input/Output Description Populated connectors. Differential clock output pairs.
SNAU118 Connector Name CLKin0/CLKin0*, CLKin1/CLKin1* Input/Output Description Populated connectors. Input The default board configuration is setup for a single-ended reference source at CLKin0* (CLKin0 pin is AC-coupled to ground). If a DC-coupled clock is used to drive either of the inputs, the high voltage level must be at least 2 volts and the low voltage no greater than 0.4 volts. Populated connector. uWire Input/Output SYNC0, SYNC1 Input 10-pin header programming interface for the board.
SNAU118 Recommended Test Equipment Power Supply The Power Supply should be a low noise power supply. Phase Noise / Spectrum Analyzer For measuring phase noise an Agilent E5052A Signal Source Analyzer is recommended. An Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the architecture of the E5052A is superior for phase noise measurements.
SNAU118 Appendix A: CodeLoader Usage CodeLoader is used to program the evaluation board with either an LPT port using the included CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from http://www.ti.com/. The part number is USB2UWIRE-IFACE. Port Setup Tab Figure 9 - Port Setup tab On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that will be used to program the device on the evaluation board.
SNAU118 Clock Outputs Tab Figure 10 - Clock Outputs tab The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock mode (Bypass/Divided/Delayed/Divided & Delayed – for outputs 12 and 13), set the clock output delay value (if delay is enabled for outputs 12 and 13 only), and the clock output divider value (2, 4, 6, …, 510 for clock outputs 12 and 13 or 1-8 for clock outputs 0 - 11).
SNAU118 Bits/Pins Tab Figure 11 - Bits/Pins tab. The Bits/Pins tab allows the user to program bits directly. Many of which are not available on other tabs. Refer to the datasheet for more detailed information. The bits available are: Common Box o RESET - Set the reset bit. This will reset the device. In a normal application it is not necessary to program this bit clear since it is auto-clearing.
SNAU118 Registers Tab The registers tab shows the value of each register. This is convenient for programming the device to the desired settings, then recording the hex values for programming in your own application. The “Export register values in hex to text file” button will allow these register values to be saved to a text file. By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’ and ‘0.
SNAU118 Appendix B: Typical Phase Noise Performance Plots Clock Outputs The LMK01801 Family features LVDS, LVPECL, 2VPECL, and LVCMOS types of outputs. Include are the phase noise plots for the following outputs.
SNAU118 LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 1 Phase Noise with Output Divider = 1 ‐80 ‐90 ‐100 Wenzel 100 MHz XTAL ‐110 CLKout8_2VPECL ‐120 CLKout8_LVPECL ‐130 CLKout4_LVDS ‐140 CLKout4_LVCMOS(NORM/INV) ‐150 ‐160 ‐170 ‐180 10.0E+0 1.0E+3 100.0E+3 10.
SNAU118 LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 4 Phase Noise with Output Divider = 4 ‐80 ‐90 ‐100 ‐110 Wenzel 100 MHz XTAL ‐120 CLKout8_2VPECL ‐130 CLKout8_LVPECL CLKout4_LVDS ‐140 CLKout4_LVCMOS(NORM/INV) ‐150 ‐160 ‐170 ‐180 10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.
SNAU118 LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 1 Phase Noise with Divider = 1 ‐60 ‐80 ‐100 LVDS /1 LVCMOS /1 ‐120 2VPECL /1 LVPECL /1 ‐140 SMHU ‐160 ‐180 10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 Figure 14 - LMK01801 Phase Noise @ 983.
SNAU118 LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 4 Phase Noise with Divider = 4 ‐60 ‐80 ‐100 LVDS /4 LVCMOS /4 ‐120 2VPECL /4 LVPECL /4 ‐140 SMHU ‐160 ‐180 10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 Figure 15 - LMK01801 Phase Noise @ 983.
SNAU118 Phase Noise Measurement Power Supply ! Signal Source LMK01801 RF Output @ 1 GHz, 0dBm CLKin0 or CLKin1 CLKoutX / CLKoutX * Agilent 5052A Figure 16 - Phase Noise Measurement Set-Up The phase noise of the signal source will impact the measured phase noise of the LMK01801. Noisy Signal Source! Clean Signal Source! Figure 17 - Noisy vs.
SNAU118 LMK01801 Sample Output Waveforms A B C D Figure 18 - LMK01801 Sample Clock Output Waveforms The output waveforms shown in Figure 18 were taken at a clock in frequency of 122.88 MHz, AC coupled. These measurements follow the VID voltage convention – See Appendix G: Differential Voltage Measurement Terminology for more information.
SNAU118 LMK01801 Analog Delay Sample Data The sample analog delay data was taken at a clock in frequency of 122.88 MHz, output format of 2VPECL. Notice in Figure 19 that with analog delay enabled there is approximately 460 ps of delay. Then in Figure 20 we added 100 ps of delay and the resulting delay is approximately 550 ps.
SNAU118 Figure 20 - CLKout12 with 100 pSec of delay relative to CLKout13 27 LMK01801BEVAL Evaluation Board Operating Instructions
SNAU118 Appendix C: Schematics Power 1 Vcc Vcc 2 R329 VccCLKoutPlaneA Vcc2 TESTPOINT 1000 SMA R332 A J1 1 2 3 4 5 6 Direct Power VccTP TERMBLOCK_2 C313 1µF C314 0.1µF C319 10µF C320 1µF C321 0.1µF C54 10µF C55 1µF C56 0.1µF DNP R330 DNP 1000 VccCLKoutPlaneA VccCLKoutPlaneA 0 C318 0.1µF VccCLKoutPlaneB R333 DNP 1000 DNPC322 DNPC323 DNPC324 10µF 1µF 0.1µF R334 1000 R335 C325 1µF C326 DNPC327 0.1µF 0.01µF C328 1µF C329 DNPC330 0.1µF 0.
LMK01801BEVAL schematic. Refer to BOM for differences. SNAU118 Main 1 2 3 4 5 6 IC_SYNC1 Vcc8_Digital Vcc7_CLKout_CG3 R310 Vcc6_CLKin1 51.
SNAU118 Inputs 1 2 3 4 CLKin0 V_LM5900 R301 SMA 0 C304 0.1µF DNPC300 0.68µF TESTPOINT C301 0.1µF 2 3 R302 39k R303 1000 R304 DNP 0 R305 0 VCXO_GND R2 1000 CLKin0* CLKin0_4_N U2 1 Vtune Vcc NC DNP NC GND OUT 6 5 C302 0.1µF C5 1µF R4 CLKin0_3_N DNPC3 0.1µF C303 10µF CLKin0_2_N 0 0 SMA C4 100pF R1 DNP 0 R3 3 4 2 1 VCXO_GND PD CLKin0_N 0 S NC DNPSCT P C1 R5 R6 DNP 270 B1 CVHD-950-122.88 122.
SNAU118 Inputs Page 2 1 2 3 VccCLKoutPlaneB VccCLKoutPlaneA LEuWire_TP TESTPOINT IC_SYNC1 R307 DNP 27k A uWire_SYNC1 TYPE2 2 4 6 R309 15k R312 27k 5 1 3 5 SYNC1_TP TESTPOINT IC_uWireLE SYNC1 VccCLKoutPlaneA R306 DNP 27k R308 DivVal2 1 3 5 2 4 6 HEADER_2X3 SMA A 15k DNP DNPC305 33pF HEADER_2X3 DNPC306 33pF R311 27k Placehold for 50 ohm resistor cose to IC on Core Schematic page. uWire_CLK or DivValue1 CLKuWire_TP VccCLKoutPlaneA For use with high frequency SYNC signals.
SNAU118 Clock Outputs Page 1 1 2 3 4 5 6 A A CLKout0 CLKout1 Default: LVPECL, AC coupled VccCLKoutPlaneA R25 DNP 120 VccCLKoutPlaneA R26 DNP 82.0 R27 DNP 51.0 R28 DNP 120 CLKout0_1_P CLKout0_P R32 DNP 62 0.1µF R37 DNP 62 GND SMA GND R38 DNP 62 GND CLKout0* R43 DNP 51.0 SMA GND R48 DNP 82.0 R54 DNP 62 0.1µF R59 DNP 62 R46 51.0 SMA B Default: LVPECL, AC coupled R50 DNP 120 R52 51.0 R57 CLKout3* C19 CLKout3_1_N CLKout3_N R55 240 SMA R56 DNP 62 0.
SNAU118 Clock Outputs Page 2 1 2 3 CLKout4 A 4 CLKout5 Default: LVPECL, AC coupled VccCLKoutPlaneA R69 DNP 120 6 Default: LVPECL, AC coupled A VccCLKoutPlaneA R70 DNP 82.0 C24 R71 DNP 51.0 R72 DNP 120 R73 DNP 82.0 CLKout4 CLKout4_1_P CLKout4_P R75 240 5 0.1µF R78 DNP 62 R79 R74 51.0 CLKout5_1_N R76 240 SMA R77 0.1µF DNP 62 68 C26 CLKout4* GND B 0.1µF R86 DNP 82.0 R85 DNP 120 R87 DNP 51.0 SMA GND R88 DNP 120 R89 DNP 82.0 R90 51.0 CLKout7 R92 DNP 82.0 C30 R93 DNP 51.
SNAU118 Clock Outputs Page 3 1 2 3 4 5 VccCLKoutPlaneB CLKout8 Default: LVPECL, AC coupled R113 DNP 120 VccCLKoutPlaneB R114 DNP 82.0 CLKout9 R115 DNP 51.0 CLKout8_1_P CLKout8_P R119 240 R120 0.1µF DNP 62 Default: LVPECL, AC coupled R116 DNP 120 CLKout8 C36 A 6 R121 240 R1220.1µF DNP 62 68 C38 CLKout8* CLKout8_1_N R127 240 0.1µF R130 DNP 120 R126 DNP 62 C41 GND 0.1µF C40 CLKout8_N R131 DNP 82.0 CLKout9* CLKout9_1_N DNP R124 SMA A 68 C39 DNP R125 DNP 62 GND R118 51.
SNAU118 Appendix D: Bill of Materials Common Bill of Materials for Evaluation Boards Item Designator Description RoHS Manufacturer PartNumber Quantity CAPACITORS 1 C1, C7, C8, C10, C12, C13, C16, C17, C18, C19, C22, C23, C24, C25, C28, C29, C30, C31, C35, C36, C37, C40, C41, C42, C43, C46, C47, C48, C49, C52, C53, C56, C301, C302, C304, C314, C321 CAP, CERM, 0.
SNAU118 Item Designator Description RoHS Manufacturer PartNumber Quantity Connector, SMT, End launch SMA 50 Ohm Y Emerson Network Power 142-0701-851 19 CONN TERM BLK PCB 5.
SNAU118 25 26 27 28 29 30 31 32 R35, R36, R57, R58, R79, R80, R101, R102, R123, R124, R145, R146, R167, R168 R302 R306, R307, R311, R312, R313, R315, R316, R319, R320, R322, R323, R325, R326, R328 R308, R309, R314, R317, R321, R324, R327 R331, R335, R337, R338, R344, R347, R350, R352 R342, R353, R357 R343, R354 R345, R355 RES, 68 ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW060368R0JNEA 14 RES, 39k ohm, 5%, 0.1W, 0603 Y Vishay-Dale CRCW060339K0JNEA 1 RES, 27k ohm, 5%, 0.
SNAU118 Appendix E: Balun Information Typical Balun Frequency Response The following figure illustrates the typical frequency response of the Mini-circuit’s ADT2-1T balun.
SNAU118 Appendix F: Properly Configuring LPT Port When trying to solve any communications issue, it is convenient to program the POWERDOWN bit to confirm high/low current draw of the evaluation board or the PLL_MUX between “Logic Low” and “Logic High” LD output to confirm successful communications. LPT Driver Loading The parallel port must be configured for proper operation. To confirm that the LPT port driver is successfully loading click “LPT/USB” “Check LPT Port.
SNAU118 Figure 23 - Selecting the LPT Port Correct LPT Mode If communications are not working, then it is possible the LPT port mode is set improperly. It is recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS of the computer. Common terms for this desired parallel port mode are “Normal,” “Output,” or “AT.” It is possible to enter BIOS setup during the initial boot up sequence of the computer.
SNAU118 Appendix G: Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used.
SNAU118 Appendix H: Troubleshooting Information If the evaluation board is not behaving as expected, the most likely issues are… 1) Board communication issue 2) Incorrect Programming of the device 3) Setup Error Refer to this checklist for a practical guide on identifying/exposing possible issues. Confirm Communications Refer to Appendix F: Properly Configuring LPT Port to trouble shoot this item.
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