Datasheet

Table Of Contents

Distribution

Path

SYNC*

CLKout0

CLKout1

CLKout2

LMK01000

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SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009

Functional Description

The LMK01000 family includes a programmable divider, a phase synchronization circuit, a programmable delay,

a clock output mux, and an LVDS or LVPECL output buffer in each channel. This allows multiple integer-related

and phase-adjusted copies of the reference to be distributed to up to eight system components.

This family of devices comes in a 48-pin LLP package that is pin-to-pin and footprint compatible with other

LMK02000/LMK03000 family of clocking devices.

BIAS PIN

To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is

important for low noise performance.

CLKin0/CLKin0* and CLKin1/CLKin1 INPUT PORTS

The device can be driven either by the CLKin0/CLKin0* or the CLKin1/CLKin1* pins. The choice of which one to

use is software selectable. These input ports must be AC coupled. To drive these inputs in a single ended

fashion, AC ground the complementary input.

When choosing AC coupling capacitors for clock signals 0.1 µF is a good starting point, but lower frequencies

may require higher value capacitors while higher frequencies may use lower value capacitors.

CLKout DELAYS

Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a

150 ps step size and range from 0 to 2250 ps of total delay. When the delay is enabled it adds to the output

noise floor; the total additive noise is 10(log( 10^(Output Noise Floor/10) + 10^(Delay Noise Floor/10) ). Refer to

the Typical Performance Characteristics plots for the Delay Noise Floor information.

LVDS/LVPECL OUTPUTS

Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the

outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0.

GLOBAL CLOCK OUTPUT SYNCHRONIZATION

The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided

outputs are also held in a logic low state. When the SYNC* pin goes high, the divided clock outputs are activated

and will transition to a high state simultaneously. Clocks in the Bypassed state are not affected by SYNC* and

are always synchronized with the divided outputs.

The SYNC* pin must be held low for greater than one clock cycle of the Frequency Input port, also known as the

distribution path. Once this low event has been registered, the outputs will not reflect the low state for four more

cycles. When the SYNC* pin becomes high, the outputs will not simultaneously transition high until four more

distribution path clock cycles have passed. See the SYNC* timing diagram for further detail. In the timing

diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided,

CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4.

SYNC* Timing Diagram

Product Folder Links: LMK01000