Datasheet
Table Of Contents
LMK01000
www.ti.com
SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009
Electrical Characteristics
(1)
(continued)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T
A
≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most
likely parametric norms at Vcc = 3.3 V, T
A
= 25 °C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed).
Symbol Parameter Conditions Min Typ Max Units
Equal loading and identical
t
SKEW
CLKoutX to CLKoutY
(4)
clock configuration -30 ±4 30 ps
R
L
= 100 Ω
Vboost=0 250 350 450
V
OD
Differential Output Voltage
(6)
mV
Vboost=1 390
Change in magnitude of V
OD
for complementary
ΔV
OD
R
L
= 100 Ω -50 50 mV
output states
1.07 1.37
V
OS
Output Offset Voltage R
L
= 100 Ω 1.25 V
0 0
Change in magnitude of V
OS
for complementary
ΔV
OS
R
L
= 100 Ω -35 35 mV
output states
I
SA
Clock Output Short Circuit Current Single ended outputs shorted
-24 24 mA
I
SB
single ended to GND
Clock Output Short Circuit Current Complementary outputs tied
I
SAB
-12 12 mA
differential together
Clock Distribution Section - LVPECL Clock Outputs
f
CLKoutX
=
65
R
L
= 100 Ω
200 MHz
Bandwidth =
f
CLKoutX
=
Jitter
ADD
Additive RMS Jitter
(5)
100 Hz to 20 25 fs
800 MHz
MHz
f
CLKoutX
=
Vboost = 1
25
1600 MHz
f
CLKoutX
=
-158
200 MHz
R
L
= 100 Ω f
CLKoutX
=
Noise Floor Divider Noise Floor
(7)
-154 dBc/Hz
Vboost = 1 800 MHz
f
CLKoutX
=
-148
1600 MHz
Equal loading and identical
clock configuration
t
SKEW
CLKoutX to CLKoutY
(8)
-30 ±3 30 ps
Termination = 50 Ω to Vcc - 2
V
Vcc -
V
OH
Output High Voltage V
0.98
Termination = 50 Ω to Vcc - 2
V
Vcc -
V
OL
Output Low Voltage V
1.8
Vboost = 0 660 810 965
V
OD
Differential Output Voltage
(9)
mV
Vboost = 1 865
Digital LVTTL Interfaces
(10)
V
IH
High-Level Input Voltage 2.0 Vcc V
V
IL
Low-Level Input Voltage 0.8 V
I
IH
High-Level Input Current V
IH
= Vcc -5.0 5.0 µA
I
IL
Low-Level Input Current V
IL
= 0 -40.0 5.0 µA
Vcc -
V
OH
High-Level Output Voltage I
OH
= +500 µA V
0.4
V
OL
Low-Level Output Voltage I
OL
= -500 µA 0.4 V
(6) See characterization plots to see how this parameter varies over frequency.
(7) The noise floor of the divider is measured as the far out phase noise of the divider. Typically this offset is 40 MHz, but for lower
frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. If the delay is used, then use
section 1.3.
(8) Specification is guaranteed by characterization and is not tested in production.
(9) See characterization plots to see how this parameter varies over frequency.
(10) Applies to GOE, LD, and SYNC*.
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LMK01000