Datasheet

LMK01000
www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009
Package Thermal Resistance
Package θ
JA
θ
J-PAD (Thermal Pad)
48-Lead LLP
(1)
27.4° C/W 5.8° C/W
(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These
vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in
the board layout.
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