Datasheet
Table Of Contents
GND
NC
Vcc1
Vcc2
Vcc3
Vcc4
Vcc5
Vcc6
Vcc7
Vcc8
Vcc9
Vcc10
Vcc11
Vcc12
Vcc13
Vcc14
CLKPWire
DATAPWire
LEPWire
NC
NC
NC
GOE
Test
CLKout0
CLKout0*
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
GND
SYNC*
CLKin0
CLKin0*
NC
CLKin1
CLKin1*
Bias
CLKout4
CLKout4*
CLKout5
CLKout5*
CLKout6
CLKout6*
CLKout7
CLKout7*
4748 46 45 44 43 42 41 40 39 38 37
11
12
10
9
8
7
6
5
4
3
2
1
1413 15 16 17 18 19 20 21 22 23 24
26
25
27
28
29
30
31
32
33
34
35
36
DAP
LLP-48
Top Down View
LMK01000
www.ti.com
SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009
Connection Diagram
Figure 1. 48-Pin LLP Package
Pin Functions
Pin Descriptions
Pin # Pin Name I/O Description
1, 25 GND - Ground
2, 7, 9,10, 32 NC - No Connect. Pin is not connected to the die.
3, 8, 13, 16, 19, 22, 26, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8,
- Power Supply
30, 31, 33, 37, 40, 43, 46 Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14
4 CLKuWire I MICROWIRE Clock Input
5 DATAuWire I MICROWIRE Data Input
6 LEuWire I MICROWIRE Latch Enable Input
11 GOE I Global Output Enable
This is an output pin used strictly for test purposes
and should be not connected for normal operation.
12 Test O
However, any load of an impedance of more than 1
kΩ is acceptable.
14, 15 CLKout0, CLKout0* O Clock Output 0
17, 18 CLKout1, CLKout1* O Clock Output 1
20, 21 CLKout2, CLKout2* O Clock Output 2
23, 24 CLKout3, CLKout3* O Clock Output 3
27 SYNC* I Global Clock Output Synchronization
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