Datasheet

0.1 PF
0.1 PF
50:Trace
50:
LMK
Input
Clock Source
CLKoutX
CLKoutX*
120:
120:
0.1 PF
0.1 PF
50:Trace
50:
Load
50:
LVPECL
Driver
CLKoutX
CLKoutX*
82:
50:Trace
120:
Load
Vcc
82:
120:
Vcc
LVPECL
Driver
LMK01000
www.ti.com SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009
Figure 10. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent
When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and ensure a
50 Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL
receivers is 2 V (See Section 3.4.1). If the other driver is not used it should be terminated with either a proper AC
or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure
single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF
test equipment no DC bias point (0 V DC) is expected for safe and proper operation. The internal 50 Ω
termination the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 11.
When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused
driver.
Figure 11. Single-Ended LVPECL Operation, AC Coupling
Conversion to LVCMOS Outputs
To drive an LVCMOS input with an LMK01000 family LVDS or LVPECL output, an LVPECL/LVDS to LVCMOS
converter such as National Semiconductor's DS90LV018A, DS90LV028A, DS90LV048A, etc. is required. For
best noise performance, LVPECL provides a higher voltage swing into input of the converter.
OSCin INPUT
In addition to LVDS and LVPECL inputs, OSCin can also be driven with a sine wave. The OSCin input can be
driven single-ended or differentially with sine waves. These configurations are shown in Figure 12 and Figure 13.
Figure 12. Single-Ended Sine Wave Input
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