Datasheet

OSCin
LMX2531
100 pF
Fout
CLKin1
DATA
CLK
LE
Microcontroller
CLK
DATA
CLKuWire
DATAuWire
LE
LEuWire
LMK010X0
100 nF
100 nF
OSCin*
LEuWire
Test
Test
VrefVCO
VregBUF
VregDIG
3.3 :
4.7 PF
10 nF
0.22 :
470 nF
0.22 :
470 nF
10 nF 10 nF
VregPLL1
VregPLL2
CLKin1*
100 pF
3.0 V
VregVCO
VccVCO
VccDIG
VccBUF
VccPLL
Vtune
CPout
C1_LF
C2_LF
R2_LF
3.3 V
Vcc1
...
Vcc2
...
Vcc13 Vcc14
CE
Bias
SYNC*
GOE
CLKout0
CLKout0*
...
CLKout7
CLKout7*
To Other Devices
100 nF
LMK01000
SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com
REGISTER R14
The LMK01000 family requires register R14 to be programmed as shown in the register map (See Section 2.2).
POWERDOWN Bit -- Device Power Down
This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of
the state of any of the other bits or pins.
POWERDOWN bit Mode
0 Normal Operation (default)
1 Entire Device Powered Down
EN_CLKout_Global Bit -- Global Clock Output Enable
This bit overrides the individual CLKoutX_EN bits. When thisbit is set to 0, all clock outputs are disabled,
regardless of thestate of any of the other bits or pins.
EN_CLKout_Global bit Clock Outputs
0 All Off
1 Normal Operation (default)
CLKin_SELECT Bit -- Device CLKin Select
This bit determines which CLKin pin is used.
CLKin bit Mode
0 CLKin1 (default)
1 CLKin0
Application Information
SYSTEM LEVEL DIAGRAM
The following shows a typical application for a LMK01000 family device. In this setup the clock may be divided,
skewed, and redistributed.
Figure 2. Typical Application
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Product Folder Links: LMK01000