Datasheet

LMK01000
SNAS437G –FEBRUARY 2008–REVISED OCTOBER 2009 www.ti.com
The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin
is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock
output synchronization is not guaranteed.
CONNECTION TO LVDS OUTPUTS
LMK01000 and LMK01010 LVDS outputs can be connected in AC or DC coupling configurations; however, in DC
coupling configuration, proper conditions must be presented by the LVDS receiver. To ensure such conditions,
we recommend the usage of LVDS receivers without fail-safe or internal input bias such as National
Semiconductor's DS90LV110T. The LMK01000 family LVDS drivers provide the adequate DC bias for the LVDS
receiver. We recommend AC coupling when using LVDS receivers with fail-safe or internal input bias.
CLKout OUTPUT STATES
Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control
bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit
(EN_CLKout_Global).
All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or
EN_CLKout_Global is set to 0.
CLKoutX EN_CLKout GOE pin Clock X Output State
_EN bit _Global bit
1 1 Low Low
Don't care 0 Don't care Off
0 Don't care Don't care Off
1 1 High / No Connect Enabled
When an LVDS output is in the Off state, the outputs are at a voltage of approximately 1.5 volts. When an
LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt.
GLOBAL OUTPUT ENABLE
The GOE pin provides an internal pull-up resistor. If it is not terminated externally, the clock output states are
determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit.
POWER-ON-RESET
When supply voltage to the device increases monotonically from ground to Vcc, the power-on-reset circuit sets
all registers to their default values, which are specified in the General Programming Information section. Voltage
should be applied to all Vcc pins simultaneously.
General Programming Information
The LMK01000 family device is programmed using several 32-bit registers. The registers consist of a data field
and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the
data field DATA[27:0].
During programming, LEuWire is low and serial data is clocked in on the rising edge of clock (MSB first). When
LEuWire goes high, data is transferred to the register bank selected by the address field. Only registers R0 to R7
and R14 need to be programmed for proper device operation.
It is required to program register R14.
RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to
ensure the device is in a default state. It is not necessary to program R0 again, but if R0 is programmed again,
the reset bit is programmed clear (RESET = 0). An example programming sequence is shown below.
• Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the reset
bit is set in R0, the other R0 bits are ignored.
– If R0 is programmed again, the reset bit is programmed clear (RESET = 0).
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