Datasheet

LMK00105
SNAS579F –MARCH 2012–REVISED MAY 2013 www.ti.com
FUNCTIONAL DESCRIPTION
The LMK00105 is a 5 output LVCMOS clock fanout buffer with low additive jitter that can operate up to 200 MHz.
It features a 2:1 input multiplexer with a crystal oscillator input, single supply or dual supply (lower power)
operation, and pin-programmable device configuration. The device is offered in a 24-pin WQFN package.
V
dd
and V
ddo
Power Supplies
Separate core and output supplies allow the output buffers to operate at the same supply as the Vdd core supply
(3.3 V or 2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or 1.5 V). Compared to single-supply
operation, dual supply operation enables lower power consumption and output-level compatibility.
Bank A (CLKout0 and CLKout1) and Bank B (CLKout2 to CLKout4) may also be operated at different V
ddo
voltages, provided neither V
ddo
voltage exceeds V
dd
.
NOTE
Care should be taken to ensure the V
ddo
voltage does not exceed the Vdd voltage to
prevent turning-on the internal ESD protection circuitry.
DO NOT DISCONNECT OR GROUND ANY OF THE V
ddo
PINS as the V
ddo
pins are
internally connected within an output bank.
CLOCK INPUT
The LMK00105 has one differential input, CLKin/CLKin* and OSCin, that can be driven in different manners that
are described in the following sections.
SELECTION OF CLOCK INPUT
Clock input selection is controlled using the SEL pin as shown in Table 1. Refer to Driving the Clock Inputs for
clock input requirements. When CLKin is selected, the crystal circuit is powered down. When OSCin is selected,
the crystal oscillator will start-up and its clock will be distributed to all outputs. Refer to Crystal Interface for more
information. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal.
Table 1. Input Selection
SEL Input
0 CLKin, CLKin*
1 OSCin (Crystal Mode)
CLKin/CLKin* Pins
The LMK00105 has a differential input (CKLin/CLKin*) which can be driven single-ended or differentially. It can
accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, or other differential and single ended signals that meet the
input requirements in Electrical Characteristics and
(1)
. Refer to Driving the Clock Inputs for more details on
driving the LMK00105 inputs.
In the event that a Crystal mode is not selected and the CLKin pins do not have an AC signal applied to them,
Table 2 following will be the state of the outputs.
(1) When using differential signals with V
CM
outside of the acceptable range for the specified V
ID
, the clock must be AC coupled.
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