Datasheet
LMK00105
SNAS579F –MARCH 2012–REVISED MAY 2013
www.ti.com
Electrical Characteristics
(2.375 V ≤ Vdd ≤ 3.45 V, 1.425 ≤ Vddo ≤ Vdd, -40 °C ≤ T
A
≤ 85 °C, Differential inputs. Typical values represent most likely
parametric norms at Vdd = Vddo = 3.3 V, T
A
= 25 °C, at the Recommended Operation Conditions at the time of product
characterization and are not ensured). Test conditions are: F
test
= 100 MHz, Load = 5 pF in parallel with 50 Ω unless
otherwise stated.
Symbol Parameter Test Conditions Min Typ Max Units
Total Device Characteristics
2.5 or
Vdd Core Supply Voltage 2.375 3.45 V
3.3
1.5,1.8,
Vddo Output Supply Voltage 1.425 2.5, or Vdd V
3.3
No CLKin 16 25
I
Vdd
Core Current V
ddo
= 3.3 V, F
test
= 100 MHz 24 mA
V
ddo
= 2.5 V, F
test
= 100 MHz 20
V
ddo
= 2.5 V,
5
OE = High, F
test
= 100 MHz
I
Vddo[n]
Current for Each Output V
ddo
= 3.3 V, mA
7
OE = High, F
test
= 100 MHz
OE = Low 0.1
OE = High @ 100 MHz 48
Total Device Current with Loads on all
I
Vdd
+ I
Vddo
mA
outputs
OE = Low 16
Power Supply Ripple Rejection (PSRR)
100 kHz, 100 mVpp
Ripple Induced
PSRR Ripple Injected on -44 dBc
Phase Spur Level
V
dd
, V
ddo
= 2.5 V
Outputs
(1)
Measured between outputs,
Skew Output Skew
(2)
6 25 ps
referenced to CLKout0
C
L
= 5 pF, R
L
= 50 Ω
0.85 1.4 2.2 ns
V
dd
= 3.3 V; V
ddo
= 3.3 V
t
PD
Propagation Delay CLKin to CLKout
(2)
C
L
= 5 pF, R
L
= 50 Ω
1.1 1.8 2.8 ns
V
dd
= 2.5 V; V
ddo
= 1.5 V
C
L
= 5 pF, R
L
= 50 Ω
0.35 ns
V
dd
= 3.3 V; V
ddo
= 3.3 V
t
PD, PP
Part-to-part Skew
(2) (3)
C
L
= 5 pF, R
L
= 50 Ω
0.6 ns
V
dd
= 2.5 V; V
ddo
= 1.5 V
f
CLKout
Output Frequency
(4)
DC 200 MHz
V
dd
= 3.3 V, V
ddo
= 1.8 V, C
L
= 10 pF 250
t
Rise
Rise/Fall Time V
dd
= 2.5 V, V
ddo
= 2.5 V, C
L
= 10 pF 275 ps
V
dd
= 3.3 V, V
ddo
= 3.3 V, C
L
= 10 pF 315
V
CLKout
Low Output Low Voltage 0.1
V
Vddo-
V
CLKout
High Output High Voltage
0.1
R
CLKout
Output Resistance 50 ohm
f
CLKout
= 156.25 MHz,
t
j
RMS Additive Jitter CMOS input slew rate ≥ 2 V/ns 30 fs
C
L
= 5 pF, BW = 12 kHz to 20 MHz
(1) AC Parameters for CMOS are dependent upon output capacitive loading
(2) Parameter is specified by design, not tested in production.
(3) Part-to-part skew is calculated as the difference between the fastest and slowest tPD across multiple devices.
(4) Specified by characterization.
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