Datasheet
LMK00105
www.ti.com
SNAS579F –MARCH 2012–REVISED MAY 2013
REVISION HISTORY
Changes from Revision E (February 2013) to Revision F Page
• Added device name to title of document. ............................................................................................................................. 1
• Changed all LLP and QFN packages to WQFN throughout document. ............................................................................... 1
• Deleted optional from CLKin* pin description. And changed complimentary to complementary. ........................................ 2
• Added max limit to Output Skew parameter and added tablenote to parameter in Electrical Characteristics Table. .......... 4
• Changed typical value for both conditions of Propagation Delay in the Electrical Characteristics Table. ........................... 4
• Added Min/Max limits to both conditions of Propagation Delay parameter in Electrical Characteristics Table. .................. 4
• Changed unit value for the first condition of Part-to-part Skew from ps to ns in the Electrical Characteristics Table. ........ 4
• Changed both Max values of each Part-to-part Skew condition in Electrical Characteristics Table. ................................... 4
• Changed the Typ value of each Rise/Fall Time condition in the Electrical Characteristics Table. ...................................... 4
• Deleted V
IL
table note. .......................................................................................................................................................... 5
• Added V
I_SE
parameter and spec limits with corresponding table note to Electrical Characteristics Table. ........................ 5
• Added CLKin* column to CLKin Input vs. Output States table. Also added fourth row starting with Logic Low under
CLKin column. ....................................................................................................................................................................... 9
• Changed table title from CLKin input vs. Output States to OSCin Input vs. Output States ................................................. 9
• Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Removed extra
references to other figures. Revised to better correspond with information in Electrical Characteristics Table. ............... 10
• Deleted Figure 10 (Near End termination) and Figure 11 (Far End termination) from Driving the Clock Inputs section ... 10
• Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section. ............ 10
• Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic. ............ 10
• Deleted sentence in reference to two deleted images. ...................................................................................................... 11
• Changed link from National packaging site to TI packaging site. ....................................................................................... 14
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