Datasheet

0.2 mm, typ
1.0 mm,
typ
2.6 mm, min
LMK00105
SNAS579F MARCH 2012REVISED MAY 2013
www.ti.com
Power Supply Bypassing
The V
dd
and V
ddo
power supplies should have a high frequency bypass capacitor, such as 100 pF, placed very
close to each supply pin. Placing the bypass capacitors on the same layer as the LMK00105 improves input
sensitivity and performance. All bypass and decoupling capacitors should have short connections to the supply
and ground plane through a short trace or via to minimize series inductance.
Thermal Management
For reliability and performance reasons the die temperature should be limited to a maximum of 125°C. That is, as
an estimate, TA (ambient temperature) plus device power consumption times θ
JA
should not exceed 125°C.
The package of the device has an exposed pad that provides the primary heat removal path as well as excellent
electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land
pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
A recommended land and via pattern is shown in Figure 13. More information on soldering WQFN packages and
gerber footprints can be obtained: www.ti.com/packaging.
To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground
plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite
side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but
should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in
Figure 13 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively
dissipated.
Figure 13. Recommended Land and Via Pattern
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