Datasheet

Ripple
Source
Bias-Tee
Power
Supplies
DUT Board
Limiting
Amp
Scope
Phase Noise
Analyzer
IC
Measure 100 mV
PP
ripple on Vcco at IC
OUT
OUT
Measure single
sideband phase spur
power in dBc
Clock
Source
IN+
IN-
Vcco
Vcc
LMK00105
www.ti.com SNAS579F –MARCH 2012–REVISED MAY 2013
Power Supply Ripple Rejection
In practical system applications, power supply noise (ripple) can be generated from switching power supplies,
digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to
understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is
applied to the power supply of a clock distribution device, such as LMK00105, it can produce narrow-band phase
modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise
spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in
dBc).
For the LMK00105, power supply ripple rejection (PSRR), was measured as the single-sideband phase spur
level (in dBc) modulated onto the clock output when a ripple signal was injected onto the V
ddo
supply. The PSRR
test setup is shown in Figure 12.
Figure 12. PSRR Test Setup
A signal generator was used to inject a sinusoidal signal onto the V
ddo
supply of the DUT board, and the peak-to-
peak ripple amplitude was measured at the V
ddo
pins of the device. A limiting amplifier was used to remove
amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise
analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following
power supply ripple conditions:
• Ripple amplitude: 100 mVpp on V
ddo
= 2.5 V
• Ripple frequency: 100 kHz
Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ)
can be calculated using the measured single-sideband phase spur level (PSRR) as follows:
DJ (ps pk-pk) = [(2 * 10
(PSRR/20)
) / (π * f
clk
)] * 10
12
(5)
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