Datasheet

Levels:
VOH = 1.4V
VOL = 1.0V
IN+
IN-
RHYS
VCCI
VCCO VCCO
RHREF
VEE
Q
1/2
LMH 7322
LE
10k
50 50
50:
LE levels referred to VCCO
+
-
Q
LE
5V
+
2.5V
+
-5V
+
Signal Source
RSECL levels:
VOH = -1100 mV
VOL = -1500 mV
Coupled
transmission line
PECL driver
Line Termination
IN+
IN-
RHYS
VCCI
VCCO VCCO
RHREF
VEE
Q
1/2
LMH 7322
Q
LE
10k
PECL levels:
VOH = 3.9V
VOL = 3.5V
LE levels referred to VCCO
5V
+
-5.2V
+
LE
LMH7322
www.ti.com SNOSAU8I –MARCH 2007–REVISED MARCH 2013
Interface from PECL to (RS)ECL
The conversion from PECL to RS-ECL is possible when connecting the V
CCI
pin to +5V, which allows the input
stage to handle these positive levels. The V
CCO
pin must be connected to the ground level in order to create the
RSECL levels. The high level of the output of the LMH7322 is normally 1.1V below the V
CCO
supply voltage, and
the low level is 1.5V below this supply. The output levels are now −1100 mV for the logic ‘1’ and −1500 mV for
the logic ‘0’ (see Figure 23). In the same way the V
EE
can be connected to the ECL supply voltage of −5.2V.
Figure 23. PECL TO RSECL
Interface from Analog to LVDS
As seen in Figure 24, the LMH7322 can be configured to create LVDS levels. This is done by connecting the
V
CCO
to 2.5V. As discussed before the output levels are now at V
CCO
–1.1V for the logic ‘1’ and at V
CCO
−1.5V for
the logic ‘0’. These levels of 1000 mV and 1400 mV comply with the LVDS levels. As can be seen in this setup,
an AC coupled signal via a transmission line is used. This signal is terminated with 50Ω.
Figure 24. ANALOG TO LVDS
Figure 25 shows a standard comparator setup which creates RSPECL levels because the V
CCO
supply voltage is
+5V. In this case the V
EE
pin is connected to the ground level. The V
CCI
pin is connected to the V
CCO
pin because
there is no need to use different positive supply voltages. The input signal is AC coupled to the positive input. To
maintain reliable results the input pins IN+ and IN− are biased at 1.4V through a resistive divider using a resistor
of 1 kΩ to ground and a resistor of 2.5 kΩ to the V
CC
and by adding two decoupling capacitors. Both inputs are
connected to the bias level by the use of a 10 kΩ resistor. With this input configuration the input stage can work
in a linear area with signals of approximately 3 V
PP
(see Input Voltage Range or V
RI
in the Electrical
Characteristics tables.)
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