Datasheet

LMH7322
www.ti.com SNOSAU8I –MARCH 2007–REVISED MARCH 2013
Table 2. PIN DESCRIPTIONS (continued)
Pin Name Description Comment
8. INA+ Positive Input part A Input for analog voltages between 200 mV below VEEA and 2V below
VCCIA.
9. RHREFA Reference Voltage Hysteresis part A The hysteresis voltage is determined by connecting a resistor from this
Resistor pin to RHYSA.
10. RHREFB Reference Voltage Hysteresis part B The hysteresis voltage is determined by connecting a resistor from this
Resistor pin to RHYSB.
11. INB+ Positive Input part B Input for analog voltages between 200 mV below VEEB and 2V below
VCCIB.
12. INB− Negative Input part B Input for analog voltages between 200 mV below VEEB and 2V below
VCCIB.
13. RHYSB Hysteresis Resistor part B The hysteresis voltage is determined by connecting a resistor from this
pin to RHREFB.
14. VCCIB Positive Supply for Input Stage part B The supply pin for the input stage is independent of the supply for the
output stage.
15. VEEB Negative Supply part B The supply pin for the negative supply is connected to the VEEA via a
string of two anti-parallel diodes (see Figure 17).
16. LEB Latch Enable Input Not part B Logic ‘0’ sets the part on hold. Logic levels are RSPECL compatible.
17. LEB Latch Enable Input Logic part B ‘1’ sets the part on hold. Logic levels are RSPECL compatible.
18. VCCOB Positive Supply for Output part B The supply pin for the output stage is independent of the supply pin for
Stage the input pin. This allows output levels of different logic families.
19. QB Inverted Output part B Output levels are determined by the choice of VCCOB.
20. QB Output part B Output levels are determined by the choice of VCCOB.
21. VCCOB Positive Supply for Output part B See other VCCOB
Stage
22. VCCOA Positive Supply for Output part A See other VCCOA.
Stage
23. QA Output part A Output levels are determined by the choice of VCCOA.
24. QA Inverted Output part A Output levels are determined by the choice of VCCOA.
25. DAP Central pad at the bottom of the A & B This pad is connected to the VEE pins and its purpose is to transfer
package heat outside the part.
Tips & Tricks Using the LMH7322
In this section several aspects are discussed concerning special applications using the LMH7322.
This concerns the LE function, the connection of the DAP in conjunction to the V
EE
pins and the use of this part
as an interface between several logic families.
The Latch Enable Pins
The latch function is intended to stop the device from comparing the signals on both input pins. If the latch
function is enabled, the output is frozen and the logic information on the output pins, present at that moment, is
held until the latch function is disabled. The timing of this process can be seen in Figure 20. The input levels for
the latch pins should comply with RSPECL, but can also be driven with PECL type of signals if the minimum
supply (V
CCO
–V
EE
) is larger or equal to 3.3V. The minimum differential latch input voltage should be 100 mV.
Another possibility to set the LE function in a steady state is to connect the pins via a resistor to the power
supply. If the LE pin is connected to V
EE
via a resistor of 10 kΩ and the LE-not pin is connected via 10 kΩ to the
V
CCO
pin the part is continuously on. Since the latch input stage is referenced to V
CCO
, the resistors to set the LE
function should be connected to this voltage. This is very important when working with different voltages for V
CCI
and V
CCO
. If connected to the wrong supply, the latch function will not work.
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