Datasheet

LMH7322
www.ti.com SNOSAU8I –MARCH 2007–REVISED MARCH 2013
Table 1. Definitions (continued)
Symbol Text Description
Hyst Hysteresis Difference between the switching point ‘0’ to ‘1’ and vice versa.
I
B-LE
Latch Enable Bias Current Current flowing in or out of the input pins, when both are biased at normal PECL
levels.
I
OS-LE
Latch Enable Offset Current Difference between the input bias current of the LE and LE pin.
TC I
OS-LE
Temp Coefficient Latch Enable Offset Temperature coefficient of I
OS-LE
.
Current
V
OS-LE
Latch Enable Offset Voltage Voltage difference needed between LE and LE to place the part in the latched or
the transparent state.
TC V
OS-LE
Temp Coefficient Latch Enable Offset Temperature coefficient of V
OS-LE
.
Voltage
V
RI-LE
Latch Enable Voltage Range Voltage which can be applied to the LE input pins without damaging the device.
V
RID-LE
Latch Enable Differential Voltage Range Differential Voltage between LE and LE at which the clamp isn’t working. The
difference can be as high as the supply voltage but excessive input currents are
flowing through the clamp diodes and protection resistors.
V
OH
Output Voltage High High state single ended output voltage (Q or Q) (see Figure 34).
V
OL
Output Voltage Low Low state single ended output voltage (Q or Q) (see Figure 34).
V
OD
average of V
ODH
and V
ODL
(V
ODH
+ V
ODL
)/2.
I
VCCI
Supply Current Input Stage Supply current into the input stage.
I
VCCO
Supply Current Output Stage Supply current into the output stage while current through the load resistors is
excluded.
I
VEE
Supply Current V
EE
pin Current flowing to the negative supply pin.
TR Maximum Toggle Rate Maximum frequency at which the outputs can toggle between the nominal V
OH
and V
OL
.
PW Pulse Width Time from 50% of the rising edge of a signal to 50% of the falling edge.
t
PDH
resp t
PDL
Propagation Delay Delay time between the moment the input signal crosses the switching level L to
H and the moment the output signal crosses 50% of the rising edge of Q output
(t
PDH
), or delay time between the moment the input signal crosses the switching
level H to L and the moment the output signal crosses 50% of the falling edge of
Q output (t
PDL
).
t
PDL
resp t
PDH
Delay time between the moment the input signal crosses the switching level L to
H and the moment the output signal crosses 50% of the falling edge of Q output
(t
PDL
), or delay time between the moment the input signal crosses the switching
level H to L and the moment the output signal crosses 50% of the rising edge of
Q output (t
PDH
).
t
PDLH
Average of t
PDH
and t
PDL
.
t
PDHL
Average of t
PDL
and t
PDH
.
t
PD
Average of t
PDLH
and t
PDHL
.
t
PDHd
resp Delay time between the moment the input signal crosses the switching level L to
t
PDLd
H and the zero crossing of the rising edge of the differential output signal (t
PDHd
),
or delay time between the moment the input signal crosses the switching level H
to L and the zero crossing of the falling edge of the differential output signal
(t
PDLd
).
t
OD-disp
Input Overdrive Dispersion Change in t
PD
for different overdrive voltages at the input pins.
t
SR-disp
Input Slew Rate Dispersion Change in t
PD
for different slew rates at the input pins.
t
CM-disp
Input Common Mode Dispersion Change in t
PD
for different common mode voltages at the input pins.
Δt
PDLH
resp Q to Q Time Skew Time skew between 50% levels of the rising edge of Q output and the falling
Δt
PDHL
edge of output (Δt
PDLH
), or time skew between 50% levels of falling edge of Q
output and rising edge of Q output (Δt
PDHL
).
Δt
PD
Average Q to Q Time Skew Average of t
PDLH
and t
PDHL
for L to H and H to L transients.
ΔtP
Dd
Average Diff. Time Skew Average of t
PDHd
and t
PDLd
for L to H and H to L transients.
t
r
/ t
rd
Output Rise Time (20% - 80%) Time needed for the (single ended or differential) output voltage to change from
20% of its nominal value to 80%.
t
f
/ t
fd
Output Fall Time (20% - 80%) Time needed for the (single ended or differential) output voltage to change from
80% of its nominal value to 20%.
t
s
LE Latch Setup Time Time the input signal has to be stable before enabling the latch functionality.
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