Datasheet

Clock out

Chip Select out

Data Out (MOSI)

Data In (MISO)

Control Logic

LMH6881

CLK

SDI

SDO

Recommended:

R = 250: to 400:

For SDO (MISO) pin only:

= R x 0.010A,

= 0V

10 mA

Typ

LMH6881

www.ti.com

SNOSC72E –JUNE 2012–REVISED MARCH 2013

Figure 47. Internal Operation of the SDO pin

FIGURE OF MERIT: DYNAMIC RANGE FIGURE

The dynamic range figure (DRF) as illustrated in Figure 5, is defined as the input third order intercept point (IIP3)

minus the noise figure (NF). The combination of noise figure and linearity gives a good proxy for the total

dynamic range of an amplifier. In some ways this figure is similar to the SFDR of an analog-to-digital converter.

In contrast to an ADC, though, an amplifier will not have a full-scale input to use as a reference point. With

amplifiers, there is no one point where signal amplitude hits “full scale”. Yet, there are real limitations to how

large of a signal the amplifier can handle. Normally, the distortion products produced by the amplifier will

determine the upper limit to signal amplitude. The intermodulation intercept point is an imaginary point that gives

a well understood figure of merit for the maximum signal an amplifier can handle. For low-amplitude signals the

noise figure gives a threshold of the lowest signal that the amplifier can reproduce. By combining the third-order

input intercepts point and the noise figure the DRF gives a very good indication of the available dynamic range

offered.

POWER SUPPLY CONSIDERATIONS

The LMH6881 was designed to be operated on 5-V power supplies. The voltage range for VCC is 4.75 V to 5.25

V. Power-supply accuracy of 5% or better is advised. When operated on a board with high-speed digital signals it

is important to provide isolation between digital signal noise and the analog input pins. The SP16160CH1RB

reference board provides an example of good board layout.

The power supply pins are 19, 20, 23 and 24. Each supply pin should be decoupled with a low-inductance,

surface-mount ceramic capacitor of approximately 10 nF as close to the device as possible. When vias are used

to connect the bypass capacitors to a ground plane the vias should be configured for minimal parasitic

inductance. One method of reducing via inductance is to use multiple vias. For broadband systems two

capacitors per supply pin are advised.

To avoid undesirable signal transients the LMH6881 should not be powered on with large inputs signals present.

Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs when an

ADC is used in the application.

Product Folder Links: LMH6881