Datasheet

SCLK
SCSb
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
R/Wb A3 A2 A1 A00 0 0
D7 D6 D5 D4 D3 D2 D1 D0C7 C6 C5 C4 C3 C2 C1 C0
Reserved (3-bits)
(MSB) (LSB)
COMMAND FIELD DATA FIELD
Address (4-bits)
Write DATA
SDI
SDO
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
Data (8-bits)
Read DATA
Single Access Cycle
LMH6881
SNOSC72E –JUNE 2012–REVISED MARCH 2013 www.ti.com
Table 4. SPI Registers
Address Read/Write Name Description Default value [Hex]
0 R Revision ID Revision of the product 1 (first revision)
1 R Product ID Identification of the 20
product
2 R/W Power down Power up/down of the 0
amplifier
3 R/W Attenuation Attenuation control 50
Table 5. Register 2 Definition
7 6 5 4 3 2 1 0
Reserved OFF = 1,1: ON = 0,0 Reserved
Table 6. Register 3 Definition
7 6 5 4 3 2 1 0
Reserved 16dB 8dB 4dB 2dB 1dB 0.5dB 0.25dB
Gain [dB] = 26- (Register3 * 0.25); valid range is 0 to 80 in decimal.
Figure 46. Serial Interface Protocol (SPI Compatible)
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