Datasheet

LMH6881

SNOSC72E –JUNE 2012–REVISED MARCH 2013

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PARALLEL INTERFACE

Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space

dedicated to control lines. To place the LMH6881 into parallel mode the SPI pin (pin 5) is set to the logical zero

state. Alternately the SPI pin can be connected directly to ground. The SPI pin has a weak internal resistor to

ground. If left unconnected, the amplifier will operate in parallel mode.

In parallel mode the gain can be changed in 2-dB steps with a 4-bit gain control bus. The attenuator control pins

are internally biased to logic high state with weak pull-up resistors, with the exception of D0 which is biased low

due to the shared SDO function. If the control bus is left unconnected, the amplifier gain will be set to 6 dB.

Table 3 shows the gain of the amplifier when controlled in parallel mode.

Table 3. Amplifier Gain for All Control Pin Combinations

Control pins logical level in parallel mode

D3 D2 D1 D0 Decimal value Amplifier voltage

gain [dB]

1 X 1 X 10 - 15 6

1 0 0 1 9 8

1 0 0 0 8 10

0 1 1 1 7 12

0 1 1 0 6 14

0 1 0 1 5 16

0 1 0 0 4 18

0 0 1 1 3 20

0 0 1 0 2 22

0 0 0 1 1 24

0 0 0 0 0 26

For fixed-gain applications the attenuator-control pins should be connected to the desired logic state instead of

relying on the weak internal bias. Data from the gain-control pins directly drive the amplifier gain circuits. To

minimize gain change glitches all gain pins should be driven with minimal skew. If gain-pin timing is uncertain,

undesirable transients can be avoided by using the shutdown pin to disable the amplifier while the gain is

changed. Gain glitches are most likely to occur when multiple bits change value for a small gain change, such as

the gain change from 10 dB to 12 dB which requires changing all 4 gain-control pins.

A shutdown pin (SD == 0, amplifier on, SD == 1, amplifier off) is provided to reduce power consumption by

disabling the highest power portions of the amplifier. The digital control circuit is not shut down and will preserve

the last active gain setting during the disabled state. See the Typical Performance Characteristics section for

disable and enable timing information. The SD pin is functional in parallel mode only and disabled in serial mode.

Product Folder Links: LMH6881