Datasheet

+
-
R
IN
51:
R
F
560:
X1
-
+
R
ISO
51:
R
G
560:
CL
10 pF
R
L
1 k:
V
IN
LMH6703
SNOSAF2D –FEBRUARY 2005–REVISED MARCH 2013 www.ti.com
CAPACITIVE LOAD DRIVE
Figure 30. Decoupling Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor R
ISO
. Figure 30 shows
the use of a series output resistor, R
ISO
, to stabilize the amplifier output under capacitive loading. Capacitive
loads from 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible
oscillation. The chart “Suggested R
ISO
vs. Cap Load” gives a recommended value for selecting a series output
resistor for mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of
peaking in the frequency response. This produces a good compromise between settling time and bandwidth. For
applications where maximum frequency response is needed and some peaking is tolerable, the value of R
ISO
can
be reduced slightly from the recommended values.
DC ACCURACY AND NOISE
Example below shows the output offset computation equation for the non-inverting configuration (see Figure 27)
using the typical bias current and offset specifications for A
V
= + 2:
Output Offset : V
O
= (I
BN
· R
IN
± V
OS
) (1 + R
F
/R
G
) ± I
BI
· R
F
Where R
IN
is the equivalent input impedance on the non-inverting input.
Example computation for A
V
= +2, R
F
= 560Ω, R
IN
= 25Ω:
V
O
= (7 μA · 25Ω ± 1.5 mV) (1 + 560/560) ± 2μA · 560≈ −3.7 mV to 4.5 mV
A good design, however, should include a worst case calculation using Min/Max numbers in the data sheet
tables, in order to ensure "worst case" operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in
Application Note OA-07 (SNOA365). The two input bias currents are physically unrelated in both magnitude and
polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the
source impedance for the two inputs (as is commonly done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage
and the two input noise currents, the output noise is developed through the same gain equations for each term
but combined as the square root of the sum of squared contributing elements. See Application Note OA-12
(SNOA375) for a full discussion of noise calculations for current feedback amplifiers.
PRINTED CIRCUIT LAYOUT
Whenever questions about layout arise, use the evaluation board as a guide. The CLC730216 is the evaluation
board for SOT-23-6 samples of the LMH6703 and the CLC730227 is the evaluation board for SOIC samples of
the LMH6703.
To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins.
Components in the feedback path should be placed as close to the device as possible to minimize parasitic
capacitance. For long signal paths controlled impedance lines should be used, along with impedance matching
elements at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each voltage rail
to ground are applied in pairs. The larger electrolytic bypass capacitors can be located further from the device,
the smaller ceramic bypass capacitors should be placed as close to the device as possible. In Figure 27 and
Figure 28 C
SS
is optional, but is recommended for best second order harmonic distortion.
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