Datasheet

LMH6702
+
-
C
IN
ADC
R
S
LMH6702
www.ti.com SNOSA03F –NOVEMBER 2002–REVISED MARCH 2013
2-TONE 3
rd
ORDER INTERMODULATION
The 2-tone, 3rd order spurious plot shows a relatively constant difference between the test power level and the
spurious level with the difference depending on frequency. The LMH6702 does not show an intercept type
performance, (where the relative spurious levels change at a 2X rate vs. the test tone powers), due to an internal
full power bandwidth enhancement circuit that boosts the performance as the output swing increases while
dissipating negligible quiescent power under low output power conditions. This feature enhances the distortion
performance and full power bandwidth to match that of much higher quiescent supply current parts.
CAPACITIVE LOAD DRIVE
Figure 30 shows a typical application using the LMH6702 to drive an ADC.
Figure 30. Input Amplifier to ADC
The series resistor, R
S
, between the amplifier output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels
of ringing in the pulse response. The plot of "R
S
and Settling Time vs. C
L
" in the Typical Performance
Characteristics section is an excellent starting point for selecting R
S
. The value derived in that plot minimizes the
step settling time into a fixed discrete capacitive load with the output driving a very light resistive load (1kΩ).
Sensitivity to capacitive loading is greatly reduced once the output is loaded more heavily. Therefore, for cases
where the output is heavily loaded, R
S
value may be reduced. The exact value may best be determined
experimentally for these cases.
In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly
loaded and some capacitance is present at the output. Due to the much higher frequency response of the
LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance
(parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this
susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be
minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high
frequency resistive loading.
Referring back to Figure 30, it must be noted that several additional constraints should be considered in driving
the capacitive input of an ADC. There is an option to increase R
S
, band-limiting at the ADC input for either noise
or Nyquist band-limiting purposes. Increasing R
S
too much, however, can induce an unacceptably large input
glitch due to switching transients coupling through from the "convert" signal. Also, C
IN
is oftentimes a voltage
dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as R
S
is
increased. Only slight adjustments up or down from the recommended R
S
value should therefore be attempted in
optimizing system performance.
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